1. State-machine structure (Mealy)
V. Sequential network design
State-machine structure (Mealy)
output depends on state and input
typically edge-triggered D flip-flops

2. State-machine structure (Moore)
V. Sequential network design
State-machine structure (Moore)
output depends on state only
typically edge-triggered D flip-flops

3. V. Sequential network design
Flip Flop : summary
D Flip flop
S-R Flip flop
J-K Flip flop
q : Current state
Q : Next state Q Q’ C D Q Q’ C S R Q Q’ C J K
Characteristic
Table
S R q Q 1 --
J K q Q 1
D q Q
0 0
0 1
1 0
1 1 1 SR q 1 d
Q = S + R’q
Characteristic
Equation JK q
Q = D 1 1 1 1 1
Q = Jq’ + K’q
Transition Table
(Excitation Table)
q Q D
0  0
0  1
1  0
1  1 1
q  Q
S R
0  0
0  1
1  0
1  1
0 d
1 0
0 1
d 0
q  Q
J K
0  0
0  1
1  0
1  1
0 d
1 d
d 1
d 0

4. V. Sequential network design
Flip Flop : summary
Characteristic table : For each input and state combination, define the
next state of the flip flop
Characteristic equation: Define the next state (Q) as a function of current state
and input to the flip flop
Transition table (excitation table): For each transition type,
define the inputs that cause the transition

5. V. Sequential network design
Major design steps
Step 1: Start from state diagram or word description
Step 2: Construct a State/Output table
Moore machine: one output per state (one output column)
Mealy machine: One output per state and for each input combination (one output column per input combination)
Step 3: Reduce the number of states in State/output table by removing redundant states (a state is redundant if for the same input combinations) it has the same next state and output as another state.
Step4: Encode the states in binary (for n states, log2n bits are required). Each bit in the code represents a flip flop.
Step5: Substitute corresponding binary codes to states in the State/Output table
Step6: Separate the state table into flip flop next state maps (one map for each bit or flip flop)
Step7: Use the flip flop next state map to derive flip flop excitation maps (this step depends on the type of flip flop used in the design)
Step8: Use the flip flop excitation maps to determine excitation equations for the flip flop (these equations define the input logic of the flip flop)
Step 9: Use the State/Output table to define the output logic circuit
Step10: Draw the circuit, including flip flop, flip flop input circuits and output circuit.

6. V. Sequential Network Design
Example 1
Step1: Problem Description (Word description)
Design a sequential machine that detects a 01 sequence. The detection of sequence sets the output, Z=1, which is reset (Z=0) only by a 00 input sequence
Note: The input is scan one bit at a time

7. V. Sequential Network Design
Example 1: STEP 1
Step1: State Transition Diagram of the sequential machine:
Recall that a State Transition Diagram consists of :
States (representated by circles)
Transitions (represented as arcs) between states
Transitions are labelled by input that cause them
Output are associated with
input labels (MEALY MACHINE)
State labels (MOORE MACHINE)

8. V. Sequential Network Design
Example 1: STEP1
State diagram of example 1 (Mealy Machine): C
1/1
C : 01 sequence detected, output set
to 1 B
0/0
B : 0 is detected, expecting a 1
1/1 A
State Description:
A : initial state (sequence does not begin)
1/0
0/0
0/1
Must detect a 00 to reset output to 0
First 0 detected, go to B to wait for second 0

9. V. Sequential Network Design
Example 1: STEP 2
State/Output table
0/0
1/1
1/0 A B C
0/1
For each (current state, input) pair, specify:
Next State
Output
State/Output table (Mealy Machine) CS
X=0
A B A
B B C
C B C
X= 1 NS
Output

10. V. Sequential Network Design
Example 1: STEP2
State diagram (Moore Machine): 1
A,0
B,0
C,1
D,1
A: Waiting for start of sequence 01 and output 0
B: 0 is detected, wait for 1 and output 0
C: Sequence 01 is detected, output 1 and wait for 00 to reset output
D: Start of 00 is detected; wait for the final 0 to reset output
when we get 0, go to B and output 0
When we get 1, go back to C to wait for 00 sequence

11. V. Sequential Network Design
Example 1: STEP 2 1
A,0
B,0
C,1
D,1
State /Output Table: NS
Output CS
X=0
X= 1
A B A
B B C
C D C 1
D B C 1

12. V. Sequential Network Design
Example 1: STEP 3
Reduce the number of states in STATE/OUTPUT table:
NO Redundant states in example 1
State /Output Table: NS CS
Output
X=0
X= 1
Output does not
Depend on input X
A B A
B B C
C D C 1
D B C 1

13. V. Sequential Network Design
Example 1: STEP 4
State Assignment: Encode the different states
There are 3 states  We need two States Variable y1 and y0
y1 is the leftmost bit (Flip flop 1)
y0 is the rightmost bit (Flip flop 0)
One possible state assignment:
A  00, B  01, C  10 : State code 11 is not used (don’t cares …)
There are many more state assignments:
For example, We could use the following assignments
A  11, B  10, C 01 : State code 00 is not used (don’t cares …)
A  10, B  11, C 00 : State code 01 is not used (don’t cares …)

14. V. Sequential Network Design
Example 1: STEP 5
Substitute State Codes in the State/output table
State assignment:
A  00, B  01, C  10 CS NS
X=0
X= 1
A B A
B B C
C B C
Output
State/Output table (Mealy Machine) CS NS
X=0
X= 1
Output
dd dd
d d
Unused state code

15. V. Sequential Network Design
Example 1: STEP 6
State/Output table (Mealy Machine) CS NS
X=0
X= 1
Output
d d d d
d d
Flip Flop Next State Maps
y1 (flip flop 1)
(y1y0) X 1
d d
Current
Next state Y1
Flip flop 1
(y1y0) X 1
d d
Current
Next state Y0
Flip flop 0
y0 (flip flop 0)
Flip flop Next state maps

16. V. Sequential Network Design
Example 1: STEP 7
Flip Flop Excitation Maps
Determine transitions of flip flop
For each transition, give the input that cause the transition
(Depends on the type of flip flops)
Assume JK flip flop for y1 and y0
(y1y0) X 1
Current
Next state Y1
Flip flop 1 (J1, K1)
J1 K1
(y1y0) X 1
d d
Current
Next state Y1
Flip flop 1 (J1, K1)
Next transition for X=0 and X=1
d d
d d
d d 0
d d d d

17. V. Sequential Network Design
Example 1: STEP 7
Flip Flop Excitation Maps
Assume JK flip flop for y1 and y0
(y1y0) X 1
Current
Next state Y0
Flip flop 0 (J0, K0)
J0 K0
(y1y0) X 1
d d
Current
Next state Y0
Flip flop 0
d d
d d 1
d d
d d d d
Next transition for X=0 and X=1

18. V. Sequential Network Design
Example 1: STEP 8
Flip Flop Excitation Equations (Input circuits of flip flops)
Derive K- Maps from excitation maps
Use K-maps to derive flip flop input equations
y1y0 X 01 00 11 10 1 J1
d d
d d
J1 = x•y0
(y1y0) X 1
d d
d d
d d 0
d d d d
Current
Next state Y1
Flip flop 1 (J1, K1)
J1 K1
J1 input
y1y0 X 01 00 11 10 1 K1
d d d
d d d
K1 = x’
K1 input

19. V. Sequential Network Design
Example 1: STEP 8
Flip Flop Excitation Equations (Input circuits of flip flops)
Derive K- Maps from excitation maps
Use K-maps to derive flip flop input equations
y1y0 X 01 00 11 10 1 J0
d d
d d
J0 = X’
(y1y0) X 1
d d
d d 1
d d
d d d d
Current
Next state Y0
Flip flop 0 (J0, K0)
J0 K0
J0 input
y1y0 X 01 00 11 10 1 K0
d d d
d d d
K0 = X
K0 input

20. V. Sequential Network Design
Example 1: STEP 9
Determine the output logic circuit
y1y0 X 01 00 11 10 1 Z d d
Z = y1 + x•y0
State/Output table (Mealy Machine) NS
Output Z
y1y0
X=0
X= 1
X=0
X= 1
K-map of output Z
dd dd
d d

21. V. Sequential Network Design
Example 1: STEP 10
Input circuit
Draw the circuit: (Flip flops and logic gates) y1 J1 Q K1
Memory components
CLK X y0 J0 Q K0
Output circuit OR Z

22. V. Sequential Network Design
Homework
Design the 01 sequence detector as a Moore machine. The ouput is reset
0 when a 00 sequence is detected.
Design the detectector using:
clocked JK flip flops
clocked D flip flops

23. V. Sequential Network Design
Example 2
Give the state diagram of a clocked sequential circuit that recognizes the input
sequence 1010, including overlapping.
For example, for the input sequence
X = , the corresponding output Z is
Z =
Overlapping
State diagram (Moore Machine): 1 1 1
A,0
B,0
C,0
D,0
E,1 1 1

24. V. Sequential Network Design
Example 3
Design a Moore synchronous sequential circuit to detect a string of
of three or more consecutive 1’s in an arbitrary input string.
Design the detectector using:
clocked JK flip flops
clocked D flip flops

25. V. Sequential Network Design
Example 4
Using D flip flops, design a Moore synchronous sequential comparator circuit
to determine which of the two multi-bits binary numbers X and Y (of equal
Length) is larger. The comparison is carried out from left
(Most Significant Bit) to right. Both MSB are used as input to the circuit.
Assume two outputs Z1Z2 such that:
Z1 = 1 if X > Y
Z2 = 1 if X < Y
Z1= Z2 = 0 if X = Y

26. V. Sequential Network Design
Example 5
Design a two-bit clocked sequential counter circuit that counts clock pulses.

27. Design examples Example1
Give the state diagram of a clocked sequential circuit that recognizes the input sequence 1010, including overlapping. For example, for the input sequence
X = , the corresponding output Z is
Z =
Example2
Design a Moore synchronous sequential circuit to detect a string of of three or more consecutive 1’s in an arbitrary input string. Design the detectector using:
clocked JK flip flops
clocked D flip flops
Example3
Using D flip flops, design a Moore synchronous sequential comparator circuit to determine which of the two multi-bits binary numbers X and Y (of equal Length) is larger. The comparison is carried out from left (Most Significant Bit) to right. Both MSB are used as input to the circuit.
Assume two outputs Z1Z2 such that:
Z1 = 1 if X > Y
Z2 = 1 if X < Y
Z1= Z2 = 0 if X = Y
Example4
Design a two-bit clocked sequential counter circuit that counts clock pulses.