1. Fast Timing Workshop Krakow, Nov 29 - Dec 1 st 2010 Part 2a

2. 2 Gary Varner

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6. 6 Design Choices Input coupling – Differential versus single-ended input – Needed analog bandwidth – Gain needed? Sampling Options – On ‐ chip PLL/DLL – External DLL – Analog transfer vs interrogate in situ ADC and readout options ADC and readout options – Sequential output select vs random access – On ‐ chip vs. off ‐ chip ADC – Serial, parallel, massively parallel

7. 7 Gary Varner Constraints - Analog Bandwidth - Switching noise - Leakage current - Deeper sampling Extensive radio array for UHE neutrinos - Super B Factory PID Upgrade – precision timing

8. 8 Gary Varner

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10. 10 Gary Varner

11. 11 Gary Varner

12. 12 Gary Varner

13. 13 Gary Varner

14. 14 Gary Varner

15. 15 Gary Varner

16. 16 Gary Varner IRS/Blab3 chips

17. 17 Gary Varner

18. 18 Gary Varner Blab 1

19. 19 Gary Varner Blab1 chip

20. 20 Gary Varner (IRS chip)

21. 21 Gary Varner (Belle2 Upgrade)

22. 22 Gary Varner HPK SL10

23. 23 Gary Varner

24. 24 Gary Varner

25. 25 Miroslav Firlej, Jakub Moron, Marek Idzik AGH University, Poland (University for Mining)

26. 26 Miroslav Firlej, Jakub Moron, Marek Idzik

27. 27 Miroslav Firlej, Jakub Moron, Marek Idzik

28. 28 Miroslav Firlej, Jakub Moron, Marek Idzik

29. 29 Miroslav Firlej, Jakub Moron, Marek Idzik

30. 30 Gary Varner, Kurtis Nishimura, Matt Andrew First detector and DAQ test results from the Univ Hawaii picosecond xray beamline FEL = very tight bunch specs ~ 1ps timing probe

31. 31 Gary Varner, Kurtis Nishimura, Matt Andrew

32. 32 Gary Varner, Kurtis Nishimura, Matt Andrew

33. 33 Gary Varner, Kurtis Nishimura, Matt Andrew

34. 34 Gary Varner, Kurtis Nishimura, Matt Andrew Phase II: Tunable, mono ‐ chromatic x ‐ ray Source Stabilized optical storage cavity Tests of new detectors: 3D, new chips

35. 35 Gary Varner, Kurtis Nishimura, Matt Andrew

36. 36 Gary Varner, Kurtis Nishimura, Matt Andrew

37. 37 Gary Varner, Kurtis Nishimura, Matt Andrew

38. 38 Gary Varner, Kurtis Nishimura, Matt Andrew