1. Verilog Descriptions of Digital Systems

2. Design Flow

3. Verilog Lab #3
Design a serial adder circuit using Verilog.  The circuit should add two 8-bit numbers, A and B. 
The result should be stored back into the A register.  Use the diagram below to guide you. 
Hint:  Write one module to describe the datapath and a second module to describe the control. 
Annotate your simvision trace output to demonstrate that the adder works correctly. 
Demonstrate by adding $45 to $10 in your testbench.

4. Serial Adder Data Path
pinB

5. Adder/Subtractor
// 4-bit full-adder (behavioral)
module fa(sum, co, a, b, ci) ;
input [3:0] a, b ;
input ci ;
output [3:0] sum ;
output co ;
assign {co, sum} = a + (ci ? ~b : b) + ci ;
endmodule

6. Serial Adder Control Logic
pinB
T0: if (!start) goto T0
T1: if (start) goto T1
T2: if (clrA) A <= 0, B <= pinB, C <= 0
T3: A <= shr(A), B <= shr(B)
T4: A <= shr(A), B <= shr(B)
T5: A <= shr(A), B <= shr(B)
T6: A <= shr(A), B <= shr(B), goto T0

7. Controller and Datapath Modules
pinB
module serial_adder_datapath(sum, sout, pinB, ctl, reset, clk) ;
output [7:0] sum ;
output sout ;
input sinB ;
input [ ] ctl ;
input reset, clk ;
endmodule
module serial_adder_control(ctl, busy, start, clrA, reset, inv_clk) ;
output [ ] ctl ;
output busy ;
input reset, start, inv_clk ;

8. Three Techniques for Building Control Units
Classical FSM
One-Hot
Decode a Counter
T0: if (!start) goto T0
T1: if (start) goto T1
T2: if (clrA) A <= 0, B <= pinB, C <= 0
T3: A <= shr(A), B <= shr(B)
T4: A <= shr(A), B <= shr(B)
T5: A <= shr(A), B <= shr(B)
T6: A <= shr(A), B <= shr(B), goto T0

9. Binary Multiplication

10. Binary Multiplier

11. ASM Chart

12. Numerical Example

13. Serial Multiplier (Verilog)
module multiplier(S, clk, clr, Bin, Qin, C, A, Q, P) ;
input S, clk, clr ;
input [4:0] Bin, Qin ;
output C ;
output [4:0] A, Q ;
output [2:0] P ;
// system registers
reg C ;
reg [4:0] A, Q, B ;
reg [2:0] P ;
reg [1:0] pstate, nstate ;
parameter T0 = 2'b00, T1= 2'b01, T2 = 2'b10, T3 = 2'b11 ;
// combinational circuit
wire Z ;
assign Z = ~|P ;
// state register process for controller
clk or negedge clr) begin
if (~clr) pstate <= T0 ;
else pstate <= nstate ;
end

14. Serial Multiplier (Continued)
// state transition process for controller
always @(S or Z or pstate) begin
case (pstate)
T0: if (S) nstate = T1; else nstate = T0 ;
T1: nstate = T2 ;
T2: nstate = T3 ;
T3: if (Z) nstate = T0; else nstate = T2 ;
endcase
end
// register transfer operations
clk) begin
T0: B <= Bin ;
T1: begin
A <= 0 ;
C <= 1 ;
P <= 5 ;
Q <= Qin ;
T2: begin
P <= P - 1 ;
if (Q[0]) {C,A} <= A + B ;
T3: begin
C <= 0 ;
A <= {C, A[4:1]} ;
Q <= {A[0], Q{4:1]} ;
endmodule

15. Serial Multiplier (Testbench)
module multiplier_tb;
reg S, clk, clr ;
reg [4:0] Bin, Qin ;
wire C ;
wire [4:0] A, Q ;
wire [2:0] P ;
// instantiate multiplier
multiplier uut(S, clk, clr, Bin, Qin, C, A, Q, P);
// generate test vectors
initial begin
#0 begin
S = 0;
clk = 0;
clr = 0 ;
end
#5 begin
S = 1; clr = 1;
Bin = 5'b10111 ;
Qin = 5'b10011 ;
#15 begin
S = 0 ;

16. Serial Multiplier (Testbench, continued)
// create dumpfile and generate clock
initial begin
$dumpfile("./multiplier.dmp") ;
$dumpflush ;
$dumpvars(2, multiplier_tb) ;
repeat (26) #5 clk = ~clk ;
end
endmodule