1. Lecture 5 EGRE 254 1/28/09

2. 2 Boolean algebra a.k.a. “switching algebra” –deals with Boolean values -- 0, 1 Positive-logic convention –analog voltages LOW, HIGH --> 0, 1 Negative logic -- seldom used Signal values denoted by variables (X, Y, FRED, etc.)

3. 3 Boolean operators Complement:X or (opposite of X) AND:X  Y OR:X + Y binary operators, described functionally by truth table.

4. 4 More definitions Literal: a variable or its complement –X, X, FRED, CS_L Expression: literals combined by AND, OR, parentheses, complementation –X+Y –P  Q  R –A + B  C –((FRED  Z) + CS_L  A  B  C + Q5)  RESET Equation: Variable = expression –P = ((FRED  Z) + CS_L  A  B  C + Q5)  RESET

5. 5 Logic symbols

6. 6 Basic Axioms A1A1’ A2A2’ A3A3’ A4A4’ A5A5’

7. 7 Proving theorems Using axioms or theorems already proven. Perfect induction – Verify theorem for all possible values of the variables. 1 variable 2 = 2 1 possible values. 0, 1 2 variables 4 = 2 2 possible values. 00, 01, 10, 11 3 variables 8 = 2 3 possible values. 000, 001, …, 111 n variables 2 n possible values. For general case of n variable we use the mathematical technique of finite induction.

8. 8 Prove T1 and T1’ T1 : X + 0 = X Proof 1a –If X = 0 then X + 0 = X by A4’ –If X = 1 then X + 0 = X by A5’ Proof 2a,b T1’: X  1 = X Proof 1b –If X = 1 then X  1= X by A4 –If X = 0 then X  1= X by A5 Proof 3b –T1’ follows from duality of T1. XX+0 X1X1 000 111

9. 9 Basic Theorems T1T1’ T2T2’ T3 Idempotent law T3’ T4T4’Same as T4 T5T5’

10. 10 Theorems T6 Commutative law T6’ T7 Associative law T7’ T8 Distributive law T8’ T9 Adsorption law T9’ T10 T10’ T11 T11’

11. 11 T8’ Not what we would expect! Proof 1: using truth table (perfect induction) XYZX+YX+ZYZ(X+Y)(X+Z)X + YZ 00000000 00101000 01010000 01111111 10011011 10111011 11011011 11111111

12. 12 T8’ Proof 2: Algebraically using proved theorems (X + Y)(X + Z) = (X+Y)X +(X+Y)Z ;Why? = XX+YX+XZ+YZ ; T6’, T8 = X+XY+XZ+YZ ; T3’, T6’ = X  1 + X(Y+Z) + YZ ; T1’, T8 = X(1+(Y+Z)) + YZ ; T8 = X  1 + YZ ; T6, T1’ = X + YZ ; T1’ Better (X + Y)(X + Z) = X + XZ + XY + YZ = X(1+Z+Y) + YZ = X + YZ Proof 3: Follows from T8 and duality.

13. 13 Algebraic Proofs T10: XY+XY’ = X(Y+Y’) = X  1 = X T10’: (X+Y)(X+Y’) = X+XY+XY’+YY’ = X(1+Y+Y’) + 0 = X(1) = X T11: XY+X’Z+YZ = XY+X’Z+(XYZ+X’YZ) = XY(1+Z) + X’Z(1+Z) = XY + X’Z T11’: Do as an exercise.

14. 14 Example using T9 (A+B)’C + (A+B)’CD’(E+F) = (A+B)’C – Treat (A+B)’C as X, treat D’(E+F) as Y Or instead of using T9 recognize that (A+B)’C + (A+B)’CD’(E+F) = (A+B)’C(1+D’(E+F)) = (A+B)’C It is not necessary to memorize all of these theorems. –Know through T5’ and couple that with your knowledge of ordinary algebra.

15. 15 XOR X  Y = XY’ + X’Y X  0 = X X  1 = X’ X  X = 0 X  X’ = 1 X  Y  Z = X  (Y  Z) = Z  X  Y XY XYXY 000 011 101 110

16. 16 How are these XOR gates used?

17. 17 DeMorgan’s Theorem These are the equations you must memorize But notice that given one it is trivial to obtain the others.

18. 18 Prove XYX’Y’X’Y’X+Y(X+Y)’ 0011101 0110010 1001010 1100010 Alternative proof. Let X = 0 then 1Y’ = (0 + Y)’ Let X = 1, then 0Y’ = (1+Y)’ = 1’ = 0

19. 19 DeMorgans Theorem in n variables

20. 20 Generalizations DeMorgan’s Theorem Duality. If then

21. 21

22. 22 Shannon’s expansion theorem Proof: Consider f(x i ) = x i ’f(0) xi + x i f(1) xi When x i = 0 then f(0) xi = 1f(0) xi + 0f(1) xi = f(0) xi When x i = 1 then f(1) xi = 0f(0) xi + 1f(1) xi = f(1) xi Thus, by perfect induction f(x i ) = x i ’f(0) xi + x i f(1) xi

23. 23 Implementation example Draw circuit directly from equations. Draw circuit using only NAND gates.

24. 24 Design example Design a 3-input majority circuit XYZF 000 001 010 011 100 101 110 111

25. 25 Design example Design a 3-input majority circuit XYZF 0000 0010 0100 0111 1000 1011 1101 1111

26. 26 Design example Design a 3-input majority circuit

27. 27 Design example Design a 3-input majority circuit XYZF 0000 0010 0100 0111 1000 1011 1101 1111

28. 28 Design example Design a 3-input majority circuit

29. 29 Example Show how to build an 8 input and gate using several two input and gates. Which is better? Why?

30. 30 Schmitt-trigger gates contain input hysteresis. Useful for interfacing to slow or noisy signals.

31. 31

32. 32 Tri-state buffers