1. Hierarchical Floorplanning of Chip Multiprocessors using Subgraph Discovery Javier de San Pedro Jordi Cortadella Antoni Roca Universitat Politècnica de Catalunya (Barcelona) Graph-TA 20141

2. Outline Introduction – Chip multiprocessors and floorplanning Hierarchical floorplanning methodology Results and conclusions Graph-TA 20142

3. What is a Chip Multiprocessor? Graph-TA 20143 Off-Chip Memory CoreCore L3 Cache CoreCoreCoreCoreCoreCore Interconnect L2 Cache L1 Cache L2 Cache L1 Cache L2 Cache L1 Cache L2 Cache RouterRouter RouterRouterRouterRouterRouterRouter RouterRouter RouterRouter

4. What is floorplanning? Graph-TA 20144 MC CC L2L2 CC L2L2 L3L3 RingRing CC L2L2 CC L2L2 RR

5. Minimizing wire length Graph-TA 20145 CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3

6. Maximizing regularity Graph-TA 20146 Reusability Design closure Reduce floorplanning cost

7. Finding repeating subgraphs Frequent subgraph discovery: Graph-TA 20147 Subdue: D. J. Cook and L. B. Holder, Graph-Based Data Mining, IEEE Intelligent Systems, 15(2), pages 32-41, 2000.

8. Example Graph-TA 20148 CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3 1.Find candidate pattern The most repeated subgraph

9. Floorplanning a pattern Graph-TA 20149 CC L2L2 rr 1.Find repeated pattern 2.Floorplan pattern CC L2L2rr L2L2 CC L2L2 rr CC L2L2L2L2 L2L2L2L2rr Multiple floorplans are generated for a single pattern CCL2L2rr L2L2 CC L2L2rr L2L2 CC L2L2 rr CC L2L2L2L2 L2L2L2L2rr CCL2L2rr L2L2 All pareto-optimal floorplans efficiently stored as a bounding curve:

10. Creating hierarchy Graph-TA 201410 CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3 1.Find candidate pattern 2.Floorplan pattern 3.Treat instances of pattern as black-boxes P1P1 P1P1 P1P1 P1P1 P1P1 CC L2L2 rr P1 is a new component type Has multiple shapes (defined by its bounding curve)

11. Hierarchical floorplanning Graph-TA 201411 rr rr RR L3L3 1.Find candidate pattern 2.Floorplan pattern 3.Treat instances of pattern as black-boxes 4.Repeat until no more patterns can be found P1P1 P1P1 P1P1 P1P1 P2P2 P2P2 P1P1 CC L2L2 rr P2P2 P1P1P1P1

12. Final floorplan Floorplanning the last pattern obtains the bounding curve for the entire chip Graph-TA 201412 RR L3L3 rrrr P2P2 P2P2 RR L3L3 rrrr P2P2 P2P2P2P2 RR L3L3 rr rr P2P2 P2P2

13. Generating multiple results Graph-TA 201413 RR L3L3 rrrr P2P2 P2P2 RR L3L3 rrrr P1P1P1P1 P1P1 P1P1 CC L2L2rr L2L2 CC L2L2rr L2L2 CC rr L2L2 L2L2 CC rr L2L2 L2L2 RR L3L3 rrrr CC L2L2rr L2L2 CC L2L2rr L2L2 CC rr L2L2 L2L2 CC rr L2L2 L2L2 RR L3L3 rrrr CC L2L2rr L2L2 CC L2L2rr L2L2 CC rr L2L2 L2L2 CC rr L2L2 L2L2 RR L3L3 rrrr

14. Example: ring of rings Graph-TA 201414

15. Example: ring of rings Graph-TA 201415

16. Graph-TA 201416 Estimated wirelength (meters)

17. Conclusions We can extract regularity from a netlist and build regular floorplans – Competitive area, wire length results – Reduce design time Future: application to other domains – High-level synthesis, logic synthesis, … Graph-TA 201417