1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 1 - Course Overview Spring 2007

2. ECE 425 Spring 2007Lecture 1 - Course Overview2 Announcements  Course Website: http://foghorn.cadlab.lafayette.edu/ece425/  Brief Lab Tomorrow in AEC 400  Reading  Wolf 1, 2.1-2.3

3. ECE 425 Spring 2007Lecture 1 - Course Overview3 Today’s Topics  Course overview  Objectives  Roadmap for the Semester  Administrative Details  VLSI Overview  Transistor Structure  Static CMOS Logic  Design Methods & Design Styles  VLSI Trends

4. ECE 425 Spring 2007Lecture 1 - Course Overview4 Course Objectives  Students should be able to…  VLSI Circuit Analysis: Understand MOS transistor operation, design eqns. Understand parasitics & perform simple calculations Understand static & dynamic CMOS logic Estimate delay of CMOS gates, networks, & long wires Estimate power consumption Understand design and operation of latches & flip/flops  CMOS Processing and Layout Understand the VLSI manufacturing process. Have an appreciation of current trends in VLSI manufacturing. Understand layout design rules. Design and analyze layouts for simple digital CMOS circuits Design and analyze hierarchical circuit layouts. Understand ASIC Layout styles.

5. ECE 425 Spring 2007Lecture 1 - Course Overview5 Course Objectives  Students should be able to… (cont’d)  VLSI System Design Understand register-transfer level design. Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL). Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL. Understand the design flows used in industrial IC design. Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation.

6. ECE 425 Spring 2007Lecture 1 - Course Overview6 Roadmap for the term: major topics  VLSI Overview   CMOS Processing & Fabrication  Components: Transistors, Wires, & Parasitics  Design Rules & Layout  Combinational Circuit Design & Layout  Sequential Circuit Design & Layout  Standard-Cell Design with CAD Tools & Verilog  Mixed Signal Concerns: D/A, A/D Conversion  Register-Transfer Design with Verilog  Design Project: Complete Chip

7. ECE 425 Spring 2007Lecture 1 - Course Overview7 Administrative Details  Grading  Take-Home Entry Exam 0%  2 In-Class Exams50%  Laboratory40%  Homeworks10%  My Schedule  ECE 425MWF 9:00-9:50, T 1:10-4:00 PM  VAST 200MW 10:00-11:50  Office HoursMWF 2-3, T 10-12 or by appointment

8. ECE 425 Spring 2007Lecture 1 - Course Overview8 Adminstrative Details (cont’d)  Prerequisites  ECE 322 - Intro. Solid State Devices & Circuits  Unofficial: ECE 211, 212 - Digital Design  Textbook  W. Wolf, Modern VLSI Design: Systems on Silicon, 3rd. ed. Prentice-Hall, 2002.  References  J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd. ed., Prentice-Hall, 2002.  N. Weste and D. Harris, CMOS VLSI Design: Addison-Wesley, 2005.  M. Ciletti, Modeling, Synthesis, and Prototyping with the Verilog HDL, Prentice-Hall, 1999.

9. ECE 425 Spring 2007Lecture 1 - Course Overview9 VLSI Overview  Common technologies  CMOS Transistors & Logic Gates  Structure  “Switch-Level” Transistor Model  Basic gates  The VLSI Design Process  Levels of Abstraction  Design steps  Design styles  VLSI Trends

10. ECE 425 Spring 2007Lecture 1 - Course Overview10 VLSI Technology Overview  Common technologies:  CMOS* (dominant technology)  Bipolar (e.g., TTL)  Bi-CMOS - hybrid Bipolar, CMOS (for high speed)  GaAs - Gallium Arsenide (for high speed)  Si-Ge - Silicon Germanium (for RF)  Key manufacturing technology: photolithography *Complementary Metal Oxide Semiconductor

11. ECE 425 Spring 2007Lecture 1 - Course Overview11 VLSI Technology - CMOS Transistors Key feature: transistor length L 2002: L=130nm 2003: L=90nm 2005: L=65nm 2007: L=45nm?

12. ECE 425 Spring 2007Lecture 1 - Course Overview12 VLSI Technology - CMOS Transitors  What they really look like - a 130nm transistor from the IBM G5 processor: Image Source: Apple Computer www.apple.com

13. ECE 425 Spring 2007Lecture 1 - Course Overview13 Transistor Switch Model  nfet or n transistor  on when gate H  "good" switch for logic L  "poor" switch for logic H  "pull-down" device  pfet or p transistor  on when gate L  "good" switch for logic H  "poor" switch for logic L  "pull-up" device

14. ECE 425 Spring 2007Lecture 1 - Course Overview14 CMOS Logic Design  Complementary transistor networks  Pullup: p transistors  Pulldown - n transistors

15. ECE 425 Spring 2007Lecture 1 - Course Overview15 CMOS Inverter Operation

16. ECE 425 Spring 2007Lecture 1 - Course Overview16 CMOS Logic Example - What’s This? P Transistors on when gate “L” N Transistors on when gate “H”

17. ECE 425 Spring 2007Lecture 1 - Course Overview17 VLSI Levels of Abstraction Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections

18. ECE 425 Spring 2007Lecture 1 - Course Overview18 The VLSI Design Process  Move from higher to lower levels of abstraction  Use CAD tools to automate parts of the process  Use hierarchy to manage complexity  Different design styles trade off:  Design time  Non-recurring engineering (NRE) cost  Unit cost  Performance  Power Consumption

19. ECE 425 Spring 2007Lecture 1 - Course Overview19 VLSI Design Tradeoffs  Non-Recurring Engineering (NRE) Costs  Design Costs  Mask “Tooling” costs  Unit Cost - related to chip size  Amount of logic  Current technology  Performance  Clock speed  Implementation  Power consumption  Power supply voltage  Clock speed

20. ECE 425 Spring 2007Lecture 1 - Course Overview20 VLSI Design Styles  Full Custom  ASIC - Application-Specific Integrated Circuit  PLD, FPGA - Programmable Logic  SoC - System-on-a-Chip

21. ECE 425 Spring 2007Lecture 1 - Course Overview21 Full Custom Design Style  Each circuit element carefully “handcrafted”  Tradeoffs  High Design Costs (huge effort!)  High NRE Cost  High Performance  Low Unit Cost (good for high volume products!)  Examples  Analog and Mixed-Signal  Microprocessor

22. ECE 425 Spring 2007Lecture 1 - Course Overview22 ASIC Design Style  Pre-designed (or pre-manufactured) components that are assembled and wired by CAD tools.  Standard cell (pre-designed cells)  Gate array (pre-manufactured cells - just add wiring)  Structured ASIC (complex function customized by wiring)  Tradeoffs  Low Design Cost  High NRE Cost (lower in Gate Array / Structured ASIC)  Medium Unit Cost  Medium Performance  Examples:  Control chip for cell phone  Graphics chips for desktop computers (e.g. nVidia, ATI)

23. ECE 425 Spring 2007Lecture 1 - Course Overview23 Programmable Logic Design Style  Pre-manufactured components with programmable interconnect wired by CAD tools  Tradeoffs  Low Design Cost  Low NRE Cost (basically 0)  Low performance  High unit cost  Examples  Network routers (e.g., Cisco)  Gibson “digital” electric guitar

24. ECE 425 Spring 2007Lecture 1 - Course Overview24 System-on-a-chip Design Style  Idea: combine several blocks  Intellectual property (IP) cores (e.g. ARM processor)  ASIC logic for special-purpose hardware  Programmable Logic (PLD, FPGA)  Analog  Tradeoffs  Medium design cost  High NRE cost  Medium performance  Medium unit cost  Examples  Consumer electronics (e.g., iPod)  Cable set-top boxes Sigmatel STMP3520 MP3 Decoder Image source: Semiconductor Insights, Inc. www.semiconductor.com

25. ECE 425 Spring 2007Lecture 1 - Course Overview25 Perspective on Design Styles  Few engineers will design custom chips  Some engineers will design ASICs & SOCs  Many engineers will design FPGA systems

26. ECE 425 Spring 2007Lecture 1 - Course Overview26 VLSI Trends: Moore’s Law  In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing:  Doubled transistor density every 18-24 months  Doubled performance every 18-24 months  History has proven Moore right  But, is the end is in sight?  Physical limitations  Economic limitations No exponential is forever, BUT Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation www.intel.com Your job is to postpone “forever”!

27. ECE 425 Spring 2007Lecture 1 - Course Overview27 Microprocessor Trends (Intel) Source: http://www.intel.com/pressroom/kits/quickreffam.htm, media reportshttp://www.intel.com/pressroom/kits/quickreffam.htm “Deep Submicron”

28. ECE 425 Spring 2007Lecture 1 - Course Overview28 Microprocessor Trends Alpha (R.I.P) P4 G4 Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com

29. ECE 425 Spring 2007Lecture 1 - Course Overview29 Microprocessor Trends (Log Scale) Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4N G4 Itanium 2 G5

30. ECE 425 Spring 2007Lecture 1 - Course Overview30 DRAM Memory Trends (Log Scale) Source: Textbook, Industry Reports

31. ECE 425 Spring 2007Lecture 1 - Course Overview31 Processor Performance Trends Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed., Morgan-Kaufmann, 2002. Vax 11/780

32. ECE 425 Spring 2007Lecture 1 - Course Overview32 Summary - Technology Trends  Processor  Logic capacityincreases ~ 30% per year  Clock frequencyincreases ~ 20% per year  Cost per functiondecreases ~20% per year  Memory  DRAM capacity: increases ~ 60% per year (4x every 3 years)  Speed: increases ~ 10% per year  Cost per bit: decreases ~25% per year Not any more!

33. ECE 425 Spring 2007Lecture 1 - Course Overview33 Gallery - Early Processors Mos Technology 6502 Intel 4004 First µP - 2300 xtors L=10µm

34. ECE 425 Spring 2007Lecture 1 - Course Overview34 Gallery - Current Processors Pentium® 4 42M transistors / 1.3-1.8GHz 49-55W L=180nm Pentium® 4 “Northwood” 55M transistors / 2-2.5GHz 55W L=0.130nm Area=131mm 2 Process Shrinks Pentium® 4 “Prescott” 125M transistors / 2.8-3.4GHz 115W L=90nm Area=112mm 2

35. ECE 425 Spring 2007Lecture 1 - Course Overview35 Gallery - Current Processors Intel Core 2 Duo “Conroe” 291M transistors / 2.67GHz / 65W L=65nm Area=143mm 2 Image courtesy Intel Corporations All Rights Reserved

36. ECE 425 Spring 2007Lecture 1 - Course Overview36 Gallery - Current Processors Image courtesy International Business Machines All Rights Reserved IBM Cell Processor 234M transistors / 2GHz / ??W L=90nm Area=221mm 2

37. ECE 425 Spring 2007Lecture 1 - Course Overview37 Gallery - Current FPGA Xilinx Virtex FPGA

38. ECE 425 Spring 2007Lecture 1 - Course Overview38 Gallery - Graphics Processor nVidia GeForce4 57M transistors / 300MHz / ??W L=0.15µm

39. ECE 425 Spring 2007Lecture 1 - Course Overview39 What we’re going to do  Chip design: MOSIS “tiny chip”

40. ECE 425 Spring 2007Lecture 1 - Course Overview40 What we’re going to do  Fabricated MOSIS “Tiny Chip”

41. ECE 425 Spring 2007Lecture 1 - Course Overview41 Die Photo - 2001 Design Project Chip Design by Ed Thomas Photo courtesy Ron Feiller, Agere

42. ECE 425 Spring 2007Lecture 1 - Course Overview42 Coming Up:  Fabrication Basics: Photolithography  Transistor Structure  Transistor Operation  CMOS Processing Steps  Layout Design