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6. 6 Figure. 01

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11. 11 (a) 8 * 8 array (b) 16 * 8 array

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13. 13 (c) The address of a 4-bit word in 3-D is row 5, column 8 (b) The address of a byte in 2-D is row 4. (a) The address of a bit is row 2 and column 2 Figure. 03

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16. 16 size is 4-bits, there are 4 data input lines (Io to I3) and 4 data output lines (Oo to O 3 ). During the write operation the data to be stored in memory and the read operation the data read from the memory and appears at the data output lines. Figure 04 (a) Diagram of a 32 * 4 memory, (b) virtual arrangement of cells into 32 4-bits words.

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19. 19 Figure -07 (a) Typical ROM block symbol (b) table showing the binary data at each address.

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22. 22 ABX 001 010 100 111

23. 23 C in AB∑CoCo 00000 00110 01010 01101 10010 10101 11001 11111

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28. 28 A 1024-bit ROM with a 256 * 4 organization based on 32 * 32 array.

29. 29 32 * 8= 256 bits 2 5 = 32, 5 address lines 16 * 16 = 256 bits (break into arrays) 2 4 = 16, 4 rows decoder remaining 1 add.. line is column decoder

30. 30 32 * 1024 * 8= 262,144 bits 2 5. 2 10 = 32,768, 15 address lines 512 * 512 = 268,144 bits (break into arrays) 2 9 = 512 bits, 4 rows decoder remaining 6 add.. line for column decoder 2 6 = 64 bits, column decoder multiple of 8.

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34. 34 SRAM Latch memory Cell

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38. 38 o Write binary 1 o Write binary 1. R/W = 0, C/R = 1 Refresh = 0, Din = 1 R/W = 0 is zero which will input will input buffer & dis able o/p buffer. C/R = 1 Din = 1 and transistor must be turn only high value of Row line. Transistor acts as a switch connecting capacitor to row. This capacitor will start charge to a +ve voltage. o Write Binary = 0 R/W = 0, R/C 1, Ref = 0, Din = 0, the capacitor will start to discharge. Read R/W = 1, Ref = 1 turning on the transistor & connect the capacitor on column line & therefore Data appears on the data out.

39. 39 o Reading. R/W, which will enable o/p buffers and disable i/p buffer. R = 1, turning on the transistor & connects the capacitor to the column line & therefore data appears on the data out line. o Refreshing. R/W = 1, Ref= 1 R= 1, The transistor turns on connecting the capacitor to the column the o/p buffer is enable & the stored charged is to the i/p of the Refresh buffer which is enabled by the high on Refresh i/p. This process produces a voltage on the bit line are column line therefore Replenishing the capacitor.

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42. 42 Problem: Expand 256 * 4 into 256* 8 ? Solution:

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45. 45 Solution: Expansion of 64K*4 ROM into 64K*16 ROM.

46. 46 Q3(c)# see in first example of ROM Architecture. Q3(d)# What is the bit capacity of a DRAM wit a 2 12 *8 organization? Solution: The total capacity is found by, 2 12 *8 = 4096*8 2 12 *8 = 32,768 bits Paper of 2011 Exam 10-Batch Electronics. Q4(a)# Explain the difference between SRAM & DRAM memory technology with the help of basic diagram? Static RAM: Dynamic RAM It is made up of Latches.It is made of Capacitors. It is bigger in size has high cost.It is small in size has low cost. It has less capacity b/c it is madeIt has more capacity to store of latches.Data b/c it is made of capacitor.

47. 47 SRAM has faster Access timeDRAM has slowest Access time. SRAM cell DRAM cell Q4(d)# Construct a internal structure of ROM 4K*8 IC ? Design is in next slides…

48. 48 Internal structure of ROM 4K*8 IC…