1. Reliable Data Processor in VLSI
Senior Capstone Project
Presented By Rahul Chopra
May 7th 2002
Advisor: Dr. Vinod Prasad
Abstract:
The Reliable Data Processor in VLSI is a user driven data processor that carries out Arithmetic and Logic operations such as AND, OR, XOR, NAND and ADD on 4-bit data. The basic system consists of a 4-bit ALU controlled by a user driven controller. The system has feedback capabilities and receives feedback from an external reliable chip indicating any erroneous data transfer. Applications of the data processor include Digital Signal Processing and data encryption.

2. Overview Functional Description Block Diagram Subsystems
Controller (3*8 Decoder)
7 bit Encoder
Data Registers, D-FF with Set/Reset
ALU
P-Spice Results
Expo VHDL/FPGA Implementation
Conclusions/Future Developments

3. Functional Description
3-Bit User Input to Controller
Decodes User input, Controls ALU
ALU-Boolean and Arithmetic Operations on 4-bit data arrays.
Encoder: 4 Bits From ALU+3 Parity Bits,
7-bit Out
Data Registers-7 D-FF’s, Store Output

4. External Error Detection/Reliable
Block Diagram
External Error Detection/Reliable
Chip
Feedback
Controller
User
Select Lines D0 D4
Encoder
ALU
Data
Registers
Input Data
4 bit Vectors
7-Bit Out

5. Controller
3*8 Decoder
D0=AND
D1=OR
D2=XOR
D3=NAND
D4=ADD

6. Encoder Adds 3 Parity Bits to 4 bit output from ALU.
6 2-Input XOR Gates Used, Design Completed in Logic Works
P1= I3(+)I5(+)I7
P2= I3(+)I6(+)I7
P4= I5(+) I6(+)I7

7. Encoder- L-Edit SimulationP1 I3 I5 I7 P2 I6 P4

8. Registers Clock Input controlled.
Feedback from external chip supplies clock input.
D-FF’s will store, send data accordingly.
Designed Using 7 D-FF’s
D-FF’s Individually Built and Tested in Logic Works and L-Edit using NAND, NOT, OR Gates.
D-FF’s with Set/Reset capabilities
Set has Higher Priority

9. Registers-D-FF’s with Set/Rst Logic Works Design and Timing

10. L-Edit Design of Registers

11. ALU Design-4 Input AND, XOR

12. AND, OR Functions- L-Edit
AND Gates
OR Gates

13. XOR, NAND - L-Edit Design
XOR Gates
NAND Gates

14. Adder Circuitry- Logic Works
2 Input XOR, AND, OR Gates

15. Adder Circuitry- L-Edit Design

16. P-Spice Simulation Results-1
NAND Function of ALU
D3 High, Input Vectors NAND 1100
ALU Output 0011
Out3
Out2
Out1
Out0 D3

17. P-Spice Simulation Results-2
ADD Function of ALU
Vectors ADD 1111 , D4 = 1
ALU Results - Carry Flag-1, Bits-1010
Carry
Out3
Out2
Out1
Out0 D4

18. P-Spice Simulation Results-3
Encoded Data for ALU Adder Operation
ALU 4 Bit Output , Encoded Out
Out7
Out6
Out5
Out4
Out3
Out2
Out1

19. Completed System Controller ALU Input Data=> ALU Out
Registers/Output
Encoder

20. Expo 2002 VHDL code written. FPGA Implementation on XC4000 chip.
Presented at Student Expo on April 12th.

21. Conclusions/Future Developments
Design Tested Successfully using P-Spice.
P-Spice cannot handle Changing Inputs, Convergence Problems Nodes approx.
Future Developments:
MOSIS Fabrication of Design.
Testing with error detection chip.
More Arithmetic Operations
Expansion to 16/32 bit ALU
Applications in Digital Signal Processing/Data Encryption

22. Questions/Comments