1. Advanced ITC Presentation A. Pogiel J. Rajski J. Tyszer

2. 2 Motivation  volume reduction higher than scan chains / channels ratio  high observability of scan cells for wide range of X-profiles  design simplicity  minimum control information Reliable test response compactor

3. 3 Outline  EDT environment  Compactor architecture  Unknown states  Scan chain selection  Experimental results  Fault diagnosis  Conclusions

4. 4 EDT architecture Compacted responses Compressed patterns  X-control  Scan  Deterministic patterns  Embedded test  Selective compaction  Direct diagnosis

5. 5 Linear selector 10235467981011 453 2 0 1

6. 6 Synthesis algorithm  Generate randomly a polynomial  Verify sharing of mask bits  Determine rank  Repeat 1÷3 for several polynomials  Accept poly with the highest rank  Repeat 1÷5 for all outputs

7. 7 Linear independence DAC 2001 specified bits 32 mask bits New

8. 8 Encoding efficiency mask bits 128 64 192 256 Scan chains:

9. 9 Diagnostic resolution Design Xs % No comp. X-PressDifference Fail ratio D10.0496.7495.601.141.5145 D20.4496.0489.326.721.9693 D30.0496.8795.201.671.5288 D41.4194.7592.881.871.4360 D52.6298.9296.862.061.1583 D60.4496.1191.674.441.7437 Overdrive: 8 1000 single stuck-at faults selected randomly The smallest mask register

10. 10 Conclusions  Compression higher than scan chains / channels ratio  Programmable scan selector  High observability of scan errors  Immune to high X-fill rates  Proven on industrial designs

11. Dariusz Czysz, Janusz Rajski, Jerzy Tyszer

12. 12 purpose Low power scheme compatible with test compression reduced switching during all scan operations preserved test quality accelerated scan shifting

13. 13 outline  EDT environment  Low power test architecture  Scan shift-in operations  Power aware decompressor  Capture and scan shift-out  Experimental results  Conclusions

14. 14 motivation 100 scan chains Scan chains observing faults Test patterns 0.9M gates 45K scan cells

15. 15 control data encoding  Constants provided on a per pattern basis  Asserting all variables turn off low power test  0 1 c 1 + c 3 + c 7 = 0 c 2 + c 4 + c 7 = 1 c 3 + c 5 + c 6 = 0 c n c n-1 … c 2 c 1 c 0

16. 16 clock gater control data Design Specified bits per cube Gated FFs by one cube FFs per specified bit FFs with gated clocks (%) D17.694212461 D27.65016570 D315.6443328491 D45.155310752 Average9.0160714568 Specified bits refer to bits provided by scan to shut off flip-flops

17. 17 experimental results – filling chains D1D2D3D4 WTM [%] LoadUnload Capture Constant Shadow register Combined WSA [%]

18. 18 filling chains & clock gating D1D2D3D4 Reduction [%] Load Unload Capture Capture – only clock gaters

19. 19 conclusions  EDT can deliver low power tests  No impact on quality  Significant reduction of test power in shift  Flexible trade-offs –power efficiency –compression –test application time