1. ECE2030 Introduction to Computer Engineering Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2. 2 Basic Shifting Shift directions –Left (multiply by 2) –Right (divide by 2) Take floor value if the result is not an integer X X,Floor value of X (or  X  ) is the greatest integer number less than or equal to X, E.g. –  5/2  = 2 –  -3/2  = -2 Shift types –Logical (or unsigned) –Arithmetic (or signed)

3. 3 Logical Shift Shift Left –MSB: Shifted out –LSB: Shifted in with a “0” –Examples: (11001011 << 1) = 10010110 (11001011 << 3) = 01011000 Shift right –MSB: Shifted in with a “0” –LSB: Shifted out –Examples: (Some ISA use triple “>” for logical right shift) (11001011 >>> 1) = 01100101 (11001011 >>> 3) = 00011001

4. 4 Arithmetic Shift Shift left –MSB: Shifted out, however, be aware of overflow/underflow –LSB: Shifted in with a “0” –Examples: (1100 << 1) = 1000 (1100 << 3) = 0000 (Incorrect!)  Underflow Shift right –MSB: Retain “sign bit” –LSB: Shifted out –Examples: (1100 >> 1) = 1110 (Retain sign bit) (1100 >> 3) = 1111 (  -4/8  = -1 )  Floor value of -0.5

5. 5 Examples of Arithmetic Shift 1111 1011 Arithmetic shift right by 1  1111 1101 1111 1011 Arithmetic shift left by 1  1111 0110 1011 1111 (= -65) Arithmetic shift left by 1 (i.e. x2)  0111 1110 (= +126  -130)  Underflow ! 0100 0010 (= +66) Arithmetic shift left by 1 (i.e. x2)  1000 0100 (= -124  +132)  Overflow ! Overflow/Underflow

6. 6 4-bit Logical Shifter S1S0D3D2D1D0 0XA3A2A1A0 100A3A2A1 11A2A1A00 A3 A2A1A0 D3 D2D1D0 S/NS S0 S1 L/R

7. 7 4-bit Logical Shifter using 4-to-1 Mux 4-to-1 Mux 00 011011 s1 s0 S1S0D3D2D1D0 0XA3A2A1A0 100A3A2A1 11A2A1A00 D3 A2A3 4-to-1 Mux 00 011011 s1 s0 D2 A1 4-to-1 Mux 00 011011 s1 s0 D1 A0 4-to-1 Mux 00 011011 s1 s0 D0 S1 S0 Right Shift Left Shift

8. 8 4-bit Arithmetic Shifter w/ 4-to-1 Mux 4-to-1 Mux 00 011011 s1 s0 S1S0D3D2D1D0 0XA3A2A1A0 10A3A3A2A1 11A2A1A00 D3 A2A3 4-to-1 Mux 00 011011 s1 s0 D2 A1 4-to-1 Mux 00 011011 s1 s0 D1 A0 4-to-1 Mux 00 011011 s1 s0 D0 S1 S0 Right Shift Left Shift

9. 9 4-bit Arithmetic Shifter w/ 4-to-1 Mux 4-to-1 Mux 00 011011 s1 s0 S1S0D3D2D1D0 0XA3A2A1A0 10A3A3A2A1 11A2A1A00 D3 A2A3 4-to-1 Mux 00 011011 s1 s0 D2 A1 4-to-1 Mux 00 011011 s1 s0 D1 A0 4-to-1 Mux 00 011011 s1 s0 D0 S1 S0 Right Shift Left Shift Overflow/Underflow

10. 10 4-bit Arithmetic Shifter w/ 4-to-1 Mux 4-to-1 Mux 00 011011 s1 s0 S1S0D3D2D1D0 0XA3A2A1A0 10A3A3A2A1 11A2A1A00 D3 A2A3 4-to-1 Mux 00 011011 s1 s0 D2 A1 4-to-1 Mux 00 011011 s1 s0 D1 A0 4-to-1 Mux 00 011011 s1 s0 D0 S1 S0 Right Shift Left Shift Overflow/Underflow Overflow Underflow Detection

11. 11 Rotator S1S0D3D2D1D0 00A3A2A1A0 01 A3A2A1 10 A0A3A2 11 A1A0A3 4-to-1 Mux 00 011011 s1 s0 D3 A2A3 4-to-1 Mux 00 011011 s1 s0 D2 A1 4-to-1 Mux 00 011011 s1 s0 D1 A0 4-to-1 Mux 00 011011 s1 s0 D0 S1 S0

12. 12 Barrel Shifter S2S1S0D3D2D1D0 000A3A2A1A0 001A3 A2A1 010A3 A2 011A3 100 A2A1A0 101A2A1A00 110A1A000 111 000 multiple bits Shift multiple bits at a time Left Shift Right Shift

13. 13 Barrel Shifter Design w/ Mux (D3) S2S1S0D3D2D1D0 000A3A2A1A0 001A3 A2A1 010A3 A2 011A3 100 A2A1A0 101A2A1A00 110A1A000 111 000 4-to-1 Mux 00 011011 s1 s0 00 011011 s1 s0 4-to-1 Mux 2-to-1 Mux 1 0 D3 A3 A2A1A0 S0 S1 S2 Replicate and change wiring of the two 4-to-1 Muxes for D2, D1 and D0

14. 14 Barrel Shifter Design Alternative (16-bit) 2 3 Shifter 2 2 Shifter 2 1 Shifter 2 0 Shifter Left/Right S3 S2 S1 S0 16 (S3 S2 S1 S0) specifies the “shift amount” in binary 16 Output Number Input Number

15. 15 Barrel Shifter Design w/ nMOSFET D3 D2 D1 D0 A3 S=0 (No Shift) S=1S=2S=3 A2 A1 A0 S=3 S=2 S=1

16. 16 A3 Barrel Shifter Design w/ nMOSFET D3 D2 D1 D0 A3 S=0 (No Shift) S=1S=2S=3 A2 A1 A0 S=3 S=2 S=1 A3 A2

17. 17 Barrel Shifter Design w/ nMOSFET D3 D2 D1 D0 A3 S=0 (No Shift)S=1S=2S=3 A2 A1 A0 S=3 S=2 S=1 = A3 = A2 = A1

18. 18 Unsigned Binary Multiply 101 (5) X 111 (7) ---------- 101 ---------- 100011 (35)

19. 19 Unsigned Integer Multiplier (2-bit) s 2-bit by 2-bit carry carry out p0 a0b0 H.A. p1 c s a1b0a0b1 H.A. c s p2p3 a1b1

20. 20 Unsigned Integer Multiplier (3-bit) 3-bit by 3-bit p0 a0b0 s F.A. p1 a1b0a0b1 0 co s ci c F.A. p2 s a2b0a1b1 co s ci c F.A. s co s ci a0b2 00 c F.A. p3 a2b1 co s ci c F.A. co s ci a1b2 0 s s s c p4 c F.A. co s ci a2b2 p5

21. 21 4-bit Unsigned Integer Multiplier a0 b0 P0 a1 b0 a0 b1 + 0 P1 a2 b0 a1 b1 + a0 b2 + 0 P2 a3 b0 a2 b1 + a1 b2 + a0 b3 + 0 P3 a3 b1 + a2 b2 + a1 b3 + 0 P4 a3 b2 + a2 b3 + P5 a3 b3 + P6 P7 a0 b0 + Cin Cout Sum AB Full Adder a0b0 

22. 22 Propagation Delay a0 b0 P0 a1 b0 a0 b1 + 0 P1 a2 b0 a1 b1 + a0 b2 + 0 P2 a3 b0 a2 b1 + a1 b2 + a0 b3 + 0 P3 a3 b1 + a2 b2 + a1 b3 + 0 P4 a3 b2 + a2 b3 + P5 a3 b3 + P6 P7 12 3 3 4 4 5 5 6 678 4x4 Delay = 8 adders 8x8 Delay = 20 adders

23. 23 a3 b3 + P7P6 Carry-Save Multiplier a0 b0 P0 a1 b0 a0 b1 + 0 P1 a2 b0 a1 b1 + a0 b2 + 0 P2 a3 b0 a2 b1 + a1 b2 + a0 b3 + 0 P3 a3 b2 + a2 b3 + P5 a3 b1 + a2 b2 a1 b3 + + 0 P4

24. 24 Propagation Delay of Carry-Save Multiplier a0 b0 P0 a3 b1 + a2 b2 a1 b3 + a3 b2 + a2 b3 + P5 a3 b3 + P7 a1 b0 a0 b1 + 0 P1 1 2 3 3 5 6 4x4 Delay = 6 adders 8x8 Delay = 14 adders a2 b0 a1 b1 + a0 b2 + 0 P2 1 2 a3 b0 a2 b1 + a1 b2 + a0 b3 + 0 P3 1 2 3 + 4 0 P6P4

25. 25 Signed Binary Multiply When the Multiplicand is negative 11101 (-3) 01001 (+9) -------------------- 11111101 00 11101 -------------------- 11100101 Maintain the sign bits of the partial product

26. 26 Signed Binary Multiply When the Multiplier is negative 01001 (+9) 11101 (-3) -------------------- 01001 -------------------- 0101101 01001 -------------------- 01110101 10111 -------------------- 111100101 (-27) At the last step, 2’s complement the multiplicand before adding

27. 27 Signed Binary Multiply When both the Multiplicand and Multiplier are negative 10111 (-9) 11101 (-3) -------------------- 1110111 10111 -------------------- 11010011 10111 -------------------- 110001011 01001 -------------------- 000011011(+27) At the last step, 2’s complement the multiplicand before adding Maintain the sign bits of the partial product

28. 28 More Examples (1) 1111 1010 (-6) 0000 0101 (+5) -------------------- 111111 1010 111110 10 -------------------- 1110 0010 (-30) Assume 8-bit numbers

29. 29 More Examples (2) 0011 (+3) 1110 (-2) -------------------- 0 0110 00 11 -------------------- 01 0010 110 1 -------------------- 1010 (-6) Assume 4-bit numbers

30. 30 More Examples (3) 1111 1100 (-4) 1110 0000 (-32) -------------------- 11 1111 1000 0000 11 1111 00 -------------------- 111 1110 1000 0000 000 0010 0 -------------------- 000 0000 1000 0000 (+128) Assume 8-bit numbers