1. CPLD-VHDL 國立新營高工 WWW.HYIVS.TNC.EDU.TW 沈慶陽

2. VHDL範例 真值表 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY true IS
Port (a,b,c:in STD_Logic;
y:out STD_Logic);
End true;
ARCHITECTURE a OF true IS
Begin
Y<=((not a) and b and (not c))
or (a and b and (not c));
End a;

3. VHDL範例 解碼器(2對4) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all;
ENTITY decoder2_4 IS
Port (s1,s0:in STD_Logic;
m0,m1,m2,m3:out STD_Logic);
End decoder2_4;
ARCHITECTURE a OF decoder2_4 IS
Begin
m0<=(not s0) and (not s1);
m1<= s0 and (not s1);
m2<= (not s0) and s1;
m3<= s0 and s1;
End a;

4. VHDL範例 4對1多工器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all;
ENTITY mux4_1 IS
Port(s1,s0,d0,d1,d2,d3:in STD_Logic;
Y:out STD_Logic);
End mux4_1;
ARCHITECTURE a OF mux4_1 IS
Begin
Y<=((not s0) and (not s1) and d0)
or (s0 and (not s1) and d1)
or ((not s0) and s1 and d2)
or (s0 and s1 and d3);
End a;

5. VHDL範例 1對4解多工器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all;
ENTITY demux1_4 IS
Port(d,s1,s0:in STD_Logic;
d0,d1,d2,d3:out STD_Logic);
End demux1_4;
ARCHITECTURE a OF demux1_4 IS
Begin
d0<= d and (not s0) and (not s1);
d1<= d and s0 and (not s1);
d2<= d and (not s0) and s1;
D3<= d and s0 and s1;
End a;

6. VHDL行為性描述—並行敘述式指令 條件式的訊號設定敘述:When – Else 訊號Y<=訊號A When (條件1) Else
訊號B When (條件2) Else
訊號C;
選擇式的訊號設定敘述:With – Select – When
With 選擇訊號 X Select
訊號Y<=訊號A When 選擇訊號X 為m,
訊號B When 選擇訊號X 為n, :
訊號Z When Others;

7. 範例:真值表使用並行敘述When-Else
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY true_table IS
Port (x:in STD_Logic_Vector(2 downto 0);
y:out STD_Logic);
End true_table;
ARCHITECTURE a OF true_table IS
Begin
Y<= ‘1’ When x=“010” Else
‘1’ when x=“110” Else
‘0’;
End a;

8. VHDL範例 解碼器(2對4)When-Else
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY decoder2_4w IS
Port (s:in Std_Logic_Vector(1 downto 0);
m0,m1,m2,m3:out Std_Logic);
End decoder2_4w;
ARCHITECTURE a OF decoder2_4w IS
Begin
m0<=‘1’ when s=“00” Else ‘0’;
m1<=‘1’ when s=“01” Else ‘0’;
m2<= ‘1’ when s=“10” Else ‘0’;
m3<= ‘1’ when s=“11”Else ‘0’;
End a;

9. 範例 具有EN的解碼器(2對4)When-Else
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY decoder2_4w IS
Port (s:in Std_Logic_Vector(1 downto 0);
en:in std_logic;
y:out Std_Logic_vector(3 downto 0));
End decoder2_4w;
ARCHITECTURE a OF decoder2_4w IS
Begin
y<="1000" when en= '1' and s="00" else
"0100" when en= '1' and s="01" else
"0010" when en= '1' and s="10" else
"0001" when en= '1' and s="11" else
"0000" ;
End a;

10. VHDL範例 4對1多工器When-Else LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all;
ENTITY mux4_1w IS
Port (s:in Std_Logic_Vector(1 downto 0);
d0,d1,d2,d3:in STD_Logic;
Y:out STD_Logic);
End mux4_1w;
ARCHITECTURE a OF mux4_1w IS
Begin
Y<= d0 When s=“00” Else
d1 When s=“01” Else
d2 When s=“10” Else
d3;
End a;

11. VHDL範例 優先權電路When-Else
LIBRARY IEEE;
use IEEE.STD_Logic_1164.all;
ENTITY priority is
port (d0,d1,d2,d3:in std_logic;
y:out std_logic_vector(1 downto 0));
end priority;
ARCHITECTURE a of priority IS
BEGIN
y <= "11" when (d3='1)' else--高優先--
"10" when (d2='1‘) else
"01" when (d1='1‘) else
"00" ; --low priority
END a;

12. VHDL範例 優先權電路When-Else
LIBRARY IEEE;
use IEEE.STD_Logic_1164.all;
ENTITY priority is
port (d:in std_logic_vector(3 downto 0);
y:out std_logic_vector(1 downto 0));
end priority;
ARCHITECTURE a of priority IS
BEGIN
y <= "11" when d(3)='1' else--高優先--
"10" when d(2)='1' else
"01" when d(1)='1' else
"00" ; --low priority
END a;

13. 範例:真值表並行敘述With-Select-When
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY true_table IS
Port (x:in STD_Logic_Vector(2 downto 0);
y:out STD_Logic);
End true_table;
ARCHITECTURE a OF true_table IS
Begin
With x Select
Y<= ‘1’ When “010”,
‘1’ When “110”,
‘0’ When Others;
End a;

14. VHDL範例 解碼器(2對4)With-Select-When
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY decoder2_4ws IS
Port (s:in Std_Logic_Vector(1 downto 0);
m:out Std_Logic_Vector(3 downto 0));
End decoder2_4ws;
ARCHITECTURE a OF decoder2_4ws IS
Begin
With s Select
m<=“0001” when “00” ,
“0010” when “01” ,
“0100” when “10”,
“1000” when “11”,
“0000” when others;
End a;
嘗試依此例作
3對8及4對16
之解碼器

15. VHDL範例 編碼器(4對2)With-Select-When
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY encoder4_2 IS
Port (d:in Std_Logic_Vector(3 downto 0);
y:out Std_Logic_Vector(1 downto 0));
End encoder4_2;
ARCHITECTURE a OF encoder4_2 IS
Begin
With d Select
y<=“00” when “0001” ,
“01” when “0010” ,
“10” when “0100”,
“11” when “1000”,
“00” when others;
End a;
嘗試依此例作
8對3及16對4
之編碼器

16. VHDL範例 七段顯示器解碼電路With-Select-When
y:out Std_Logic_Vector(6 downto 0));
End sev_seg;
ARCHITECTURE a OF sev_seg IS
Begin
With d Select
y<=“ ” when “0000” ,
“ ” when “0001” ,
“ ” when “0011”,
“ ” when “0011”,
“ ” when “0100”,
“ ” when “0101”,
“ ” when “0110”,
“ ” when “0111”,
“ ” when “1000”,
“ ” when “1001”,
“ ” when “1010”,
“ ” when “1011”,
“ ” when “1100”,
“ ” when “1101”,
“ ” when “1110”,
“ ” when “1111”,
“ ” when others;
End a;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY sev_seg IS
Port (d:in Std_Logic_Vector(3 downto 0);

17. 範例:簡易ALU設計With-Select-When
LIBRARY IEEE;
use IEEE.STD_Logic_1164.all;
use IEEE.STD_Logic_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
ENTITY alu is
port (a,b:in std_logic_vector(3 downto 0);
s:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0));
end alu;
ARCHITECTURE a of alu IS
BEGIN
With s Select
y<= (a+b) when "000",
(a-b) when "001",
(a and b) when "010",
(a or b) when "011",
not (a) when "100",
(a xor b) when "101",
a When Others;
END a;

18. 並行敘述When-Else練習 Library IEEE; use IEEE.STD_LOGIC_1164.all;
entity logic4 is
port( d0,d1,d2,d3 :IN Std_Logic;
s:IN Std_Logic_Vector(1 downto 0);
y:OUT Std_Logic);
end logic4;
architecture a of logic4 is
begin
y <= d0 when S="00" ELSE
d1 when S="01" ELSE
'1' when S="10" ELSE
(d2 AND d3);
end a;

19. 並行敘述When-Else練習 library IEEE; use IEEE.std_logic_1164.all;
entity logic5 is
port (a,b,c: in std_logic;
s: in std_logic_vector (1 downto 0);
y0,y1: out std_logic);
end logic5;
architecture a of logic5 is
begin
y0 <= (a or b) and (not c);
y1 <=(a xor b) when s= "11" else
C when s="10" else
(b and c);
end a;