1. Kameshwar K. Yadavalli, Alexei O. Orlov, Ravi K. Kummamuru, John Timler, Craig Lent, Gary Bernstein, and Gregory Snider Department of Electrical Engineering University of Notre Dame Supported by DARPA, NSF, ONR, and W. Keck Foundation Fanout in Quantum-dot Cellular Automata

2. Outline  Quantum Cellular Automata paradigm  Initial devices  Clocked QCA  Power Delay Product  Metal tunnel junction implementation  QCA latch  QCA shift register  Fanout in QCA  Summary

3. Quantum-dot Cellular Automata A cell with 4 dots 2 extra electrons and inter-dot tunneling Polarization P = +1 Bit value “1” Polarization P = -1 Bit value “0” Neighboring cells tend to align by Coulombic coupling Information encoded in charge configuration Polarization P = 1 Bit value “1” QCA simulations are available at www.nd.edu/~qcahome/

4. 0011 0110 A B C Out Binary wire Inverter Majority gate M A B C Programmable 2-input AND or OR gate. Initial QCA devices  Ground state computation  Possibility of metastable states  Lack of power gain and signal level degradation

5. Benefits of Clocked QCA  Power Gain. Energy is supplied directly to cells by the clock, not by the signal inputs alone.  Pipelined Architectures. Clocked cells in locked state acts as a memory controlled by the clock. A large QCA array can be divided into sub-arrays using phase shifted clocks.  Fanout in QCA. A single latch can drive multiple latches to create a complex circuit.  Adiabatic clocking with reversible computation can beat the limit of power dissipation per bit operation, kTln2.

6. Implementation of Clocking in Quantum-dot Cellular Automata  Lent et al., Physics and Computation Conference, Nov. 1994  Likharev and Korotkov, Science 273, 763, 1996 Metallic or molecular dots: Clocking achieved by modulating the energy of a third dot P= +1P= –1Null State Semiconductor dots: Clocking achieved by modulating inter-dot barriers Clock signals need not have to be sent to individual cells, but to sub-arrays of cells.

7. Clocking in QCA 0 1 0 energy x Clock Clock Applied but Information is preserved! 0 Keyes and Landauer, IBM Journal of Res. Dev. 14, 152, 1970 Initial State With clock applied Null State Differential Input applied Clock barrier is slowly raised Input removed

8. Switching Energy in QCA Quasi-adiabatic operation of QCA devices leads to very low power dissipation.

9. QCA Latch: A Building Block +V IN -V IN ~ A VgVg SEM Micrograph of a QCA latch MTJ D3 D1 D2 +V IN -V IN 1m1m Electrometer MTJ=multiple tunnel junction The third, middle dot acts as an adjustable barrier for tunneling D1 D2 D3 SET MTJ

10. Experiment: Single-Electron Latch in Action  Weak input signal sets the direction of switching  Clock drives the switching  Memory Function demonstrated  Inverter Function demonstrated D1 D2 D3 E1 -V IN +V IN V CLK Latch SET electrometer Switch to “1” Hold “1” Switch to “neutral” Switch to “0” Hold “0” Switch to “neutral” Input Clock “High” T=100 mK

11. QCA Two-Stage Shift Register  Two latches with two electrometers for readout  Inter-latch coupling by means of inter-digited capacitors (C C )  A Two-phase Clock to control electron switching is used  One latch serves as input for the other 1m1m V CLK1 V CLK2 +V IN -V INCC D1D1 D2D2 D3D3 D4D4 D5D5 D6D6CC SEM micrograph

12. Operation of QCA Shift Register  Small external input applied – SR remains in neutral state  CLK1 applied 1 st latch switches. Input now can be removed  CLK2 applied 2 nd latch switches  Process is repeated for the inverted input V CLK1 V CLK2 +V IN -V IN

13. Fanout in QCA Writing Information into first stage latch Transfer information into second stage latches

14. Fanout in QCA Fanout in QCA allows for complex circuits to be designed and operated. A latch in the first stage (L1) is coupled to two latches (L2, L3) in the second stage. A two phase clock (V CLK1, V CLK2 ) controls information transfer between the two stages. Information is first written into L1, then clocked into L2, L3 on the application of V CLK2.

15. Operation of Fanout in QCA All the latches are initially in null state. A differential input is then applied to L1, to define the polarization state. On the application of V CLK1, electron switches in L1 and is locked after the input is removed. V CLK2 is then applied to L2, L3, with the locked state of L1 providing the input to L2, L3. Information from L1 is written to L2 and L3.

16. QCA with Fanout An implicit demonstration of power gain and the benefit of clocking. In the absence of clocking, there will be signal level degradation in a fanout gate. Also, the middle latch will see two kinks resulting in a higher energy state, stopping the computation. As the second stage latches are driven by a weak input, the power gain in the second stage latches is greater than unity. Kinks Enables multi-tasking architecture. Affords the creation of complex circuitry.

17. Summary  Clocked QCA offers a working paradigm for digital nanoelectronics in the quantum realm:  orders of magnitude lesser power dissipation than FETs  power gain for signal level restoration  pipelining  Latch and shift register elements for information processing  Fanout gate in QCA paradigm is demonstrated  Future Work: Molecules? High resistive junctions for QCA latches in place of MTJs, for higher charging energy  Future Work: High speed measurements on QCA

18. Fabrication of Metal-dot QCA cells  Dots = small metal (Al) islands separated by tunnel junctions (Al 2 0 3 )  Junctions: area of about 100 x 100 nm 2 ; thickness is 0.1-0.5 nm  Charging energy is small, so that operation temperature is low (<1K)  High yield and good reproducibility allows proof of concept demonstration Simple 4-dot cell is shown No clocking yet!