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CSE140L Attend discussion hours Come to lab hours Check Q&A on the website Log In to the webboard Send me

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Presentation on theme: "CSE140L Attend discussion hours Come to lab hours Check Q&A on the website Log In to the webboard Send me"— Presentation transcript:

1 CSE140L Attend discussion hours Come to lab hours Check Q&A on the website Log In to the webboard Send me email jhliu@cs.ucsd.edu

2 CSE140L About software ISE WebPack 7.1 and ModelSim XE III 6.0a in tutorials and examples If any question about older versions, come to my lab hour

3 CSE140L What ’ s the exact function of each design in Lab2? How to design the circuits?

4 CSE140L Lab2-I Shift Register What ’ s that for? 1101 0000 8:00pm 1000010010101101 1011 8:01pm8:02pm8:03pm

5 CSE140L Lab2-I Shift Register 0 0 0 0 8:00pm 1 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 11 8:01pm8:02pm8:03pm D0 D1 D2 D3 CLK Din We want We have

6 CSE140L Lab2-I Shift Register CLK D Q Din D0 D Q CLK D1 D Q CLK D2 D Q CLK D3 CLR Design Verification

7 CSE140L Lab2-II Asyn Counter 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 D0 D1 D2 D3 CLK We want We have 0 1 0 0 1 1 0 0 12345678910111213141516 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1

8 CSE140L Lab2-II Asyn Counter CLK T Q ‘ 1 ’ (VCC) D0 T Q CLK CLR Design Verification D1

9 CSE140L Lab2-III Syn Counter 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 D0 D1 D2 D3 CLK We want We have 0 1 0 0 1 1 0 0 12345678910111213141516 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 1 Combinational Logic

10 CSE140L Lab2-III Syn Counter CLK D Q D0 D Q CLK D1 D0 i = D0 ’ i-1 D1 i = D0 i-1  D1 ’ i-1 + D0 ’ i-1  D1 i-1 = D0 i-1  D1 i-1 D2 i = ? D3 i = ? D1

11 CSE140L Lab2-IV Gray Counter 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 D0 D1 D2 D3 CLK We want We have 1 1 0 0 0 1 0 0 12345678910111213141516 0 0 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 Combinational Logic

12 CSE140L Lab2-IV Gray Counter T000011110 0011 0111 1111 1011 D0D1 D2D3 T0=(D0  D1  D2  D3) ’ T200011110 001 01 111 10 D0D1 D2D3 T2=D0 ’  D1  (D2  D3) ’ T1=?T3=?

13 CSE140L Lab2-V Random Sequencer 1 1 1 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 D0 D1 D2 D3 CLK We want We have 0 0 1 1 0 0 0 1 12345678910111213141516 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 14128124936131051171514 15

14 CSE140L Lab2-V Random Sequencer CLK D Q ? D0 D Q CLK D1 D Q CLK D2 D Q CLK D3 PRE Hint

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