1. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 1 Review MODERN-WP3 S1Y2009 June 23, 2009 ST - Crolles - France

2. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 2 Outline WP3 overview Task review 3.x (on 22/06/09) –Description –Status –Next actions –Interactions Issues

3. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 3 WP3:Physical/circuit to RT-level: PV-aware and PV-robust modeling and design

4. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 4 WP3 review on 22/06/09 Not all task leaders were present General impression –Most partners started setting up the cooperation –Some issues on specification: What is expected from partners Definition of activities What are the cross-refs between tasks/WP’s –All deliverables for this year: end of M12 Eliminate potential overlap between tasks/WP2/WP5

5. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 5 T3.1: Description Task T3.1: PV-aware circuit models Process variation will be included in existing physical and symbolic circuit models. These models are essential to effectively predict delay variations in order to be able to design reliable and predictable electronic circuits. Partners: TUD, LIRM, NXP, ST-I, TUE, UNRM

6. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 6 T3.1: Status Definition of subtasks: –SbT:3.1.1: create standard cell models with support for variability –SbT:3.1.8: Optimization algorithms –SbT:3.1.9: DigCMOS high-level cell models Fast start with quick hire of personnel(3.1.1.) Good cooperation with NXP/TUE/TUD(3.1.1) Setup and training of the working group; review of recently published approaches(3.1.8) setup and training of the working group; review of existing approaches; first positive trials with basic cells(3.1.9) MOR work has started on R and RC networks

7. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 7 T3.1: next actions D3.1.1NXP, ST-I, TUD, TUE, UNRMM12 R/P: Set of alternative symbolic models for lib cells M3.1Abstract Models CMOS and AMS&RFM12 Abstract models for CMOS cell libraries reported and verified Expected deliverables is a library of executable VHDL models for a reference cell set, at month 12 (3.1.9) Specifications of individual activities Eliminate potential overlap with T3.2 NXP-MOR: For this year emphasis is on:: –Generalisation of MOR-techniques (MOR=Model Order Reduction) developed for linear circuits with SISO (Single Input-single output) to MIMO (multiple input - multiple output) –Preservation of enough sparsity of reduced matrices: We do not like to obtain a 300*300 matrix after reducing a problem of size 10k unknowns onbekenden and 300 terminals, while this large problem has a matrix with only a few non-zero elements per row (and this is sparse).

8. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 8 T3.1: interactions Strong dependencies: NXP / TUE / LIRMM Deliverable 3.1.1 will be used as input for task 3.2 from M13-24 Subtask WP3.1.8 on optimization algorithms for surrogate delay model tuning is carried out in strong cooperation with ST-I SbT3.1.9 on HDL cell models development offers points for cooperation with TUD which are going to be explored shortly.

9. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 9 T3.2: Description Task T3.2: Methodologies, tools and flows for manufacturability, testability, reliability and yield The models that will be developed in task 3.1 need to predict accurately the impact of process variation. To compensate for process variation during circuit design the PV- aware circuit models need to be used in new methods for circuit design and future design tools and flows. Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM

10. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 10 T3.2: Status NMX (??MM): defining suitable simplified circuital blocks to be used by UNGL for detailed PV simulations including some results coming from WP2 UNBO (4 MM): started work on PV compensation through adaptive body bias - characterization of ABB impact on speed and leakage power of standard cells in 45nm from STI and 32nm (predictive models – based on ITRS) NXP (0 MM): work starting in M13 UNGL (0 MM): discussion with NMX, no work started because of funding situation in UK STI (0 MM): Started exchange of technology info with UNBO, UNRM, activities will start in july 2009 UNCA (??MM): evaluate the impact of process variations on some state-of- the-art flip-flop topologies. The study is currently conducted exploiting statistical analysis on commercially available nanometer CMOS. UNRM: (??MM) Literature survey. Surrogate models of complex phenomena, based on neural networks or support vector machines, and global optimization algorithms to be employed in circuit design, have been experimented. Meetings with STI for coordination

11. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 11 T3.2: next actions D3.2.1ST-I, UNBO, UNCA, UNRMM12 R: Circuit techniques, and speed-up algorithms for PV-aware circuit simulation M3.3PV aware circuit simulation techniques3M12 PV aware circuit simulation techniques working and verified Decide on technologies to be used (link to WP2) Specify working areas, eliminate potential overlap with T3.1 and T3.3 (clear specification)

12. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 12 T3.2: interactions Input from T3.1(characterized models) is used as input for D3.2.2 (Timing analysis) Deliverable 3.2.2 (M24) will be used as input for task 3.2 from M13-24 (surrogate models and characterized libraries) D3.2.2 (Reduced param. model) will be used as input for measurments on demonstrator in WP5

13. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 13 T3.3: Description Task T3.3: PV-aware design Apart from developing models that predict impact of process variation and methods to compensate for this, there is also an approach to deal with PV by design. Solutions for PV-aware circuit design are proposed by either a monitor & control strategy or by development of low PV sensitive standard cell libraries. Inherently variability robust designs are introduced by restricted design rules, redundant/spare transistors and self- timed logic. Partners: POLI, CSEM, IFXA, LETI, NXP, UPC

14. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 14 T3.3: Status Sub-tasks defined: –3.3.1: Variability Assessment Solutions –3.3.2: Monitor and Control Strategies –3.3.3: PV-aware Circuit-Level Design Setup of simulation methodology done (IFXA,SbT3.3.1) First simulations of aging-induced variations (IFXA,SbT3.3.1) Prototype Implementation of monitor (SbT3.3.1) Modular design of sleep transistors (SbT3.3.1) Preliminary analysis of library cells (SbT3.3.2) Preliminary study of PCMOS (SbT3.3.3)

15. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 15 T3.3: next actions D3.3.1CSEM, IFXA, LETI, NXP, POLI, UPCM12 R: PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF M3.5M&C strategies for digital and AMS&RFM12 M&C strategies for digital and AMS&RF developed and verified Define models to be used (technology etc) Clarify status of NXP contribution on M&C Eliminate potential overlap with T3.2 (clear specification)

16. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 16 T3.3: interactions AMS & RF Digital 3.3.1 Variability Assessment IFXA NXP D3.3.1 3.3.2 M&C Strategies IFXA NXP POLI UPC LETI D3.3.1 D3.3.2 3.3.3 PV-aware Circuit-level design UPC CSEM D3.3.2 D3.3.3

17. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 17 T3.4: Description Task T3.4: Design for low noise and EMI/EMC Next to process variation there is also a large contribution to the timing variation from EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of AMS&RF the analogue circuits risks suffering from the digital noise. New design techniques will be proposed to suppress and canalise noise and EMI for improved reliability of the complete electrical system. Partners: NXP, LIRM, ST-I

18. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 18 T3.4: Status Subtasks defined –SbT3.4.1: Impact of supply noise, and clock distribution on EMI and circuit timing (ST-I,LIRM) –SbT3.4.2: RF-interaction models for combined PCB-package-IC. New techniques for co-habitation of RF-modules in a co-simulation environment of PCB-package-IC (NXP) –SbT3.4.3: Substrate noise monitor NFS system developped(LIRM), Paper was submitted to the VLSI- Conference and EMC Compo describing the NFS system ST I has worked on developing new design methodologies to reduce power rail noise and increase the overall system power integrity, considering all the system components, i.e., chip, package, and board. new CAD tools were identified and are under evaluation (ST-I)

19. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 19 T3.4: next actions D3.4.1LIRM, ST-IM12 R: Impact of supply noise, and clock distribution on EMI and circuit timing D3.4.2NXPM12 R: RF-interaction models for combined PCB-package-IC M3.7RF interaction models3M12 RF interaction models developed

20. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 20 T3.4: interactions Collaboration with partners: LIRM/ST-I through STMicroelectronics In France, all partners contribute to the annual deliverables Face to face meetings with: will be planned for September 2009, o.a. to discuss the LIRM NFS system Telephone calls with: held on June 19 to prepare for this presentation D5.2.1(substrate noise test chip,M12) will be use as input for SbT3.4.3

21. 23/06/2009Review MODERN-WP3 S1Y2009 Wilmar Heuvelman 21 Issues Potential overlap –Work in task 3.1 on MOR with D5.3.x : “Together with MOR (model order reduction) of interconnect parasitic (NXP), the abstract models serve for fast circuit simulation and functional block and sub-circuit exploration” –definition of compact models from WP2 and WP3.1 (clearly distinguish in review) –WP3.4: substrate noise sensor –WP3.2 and WP3.3 (no issue in tech. annex) For both subtasks(UNRM) the activity has been slightly slower than expected, due to the delay in the formal approval of the project funding in Italy: relevant expenses, such as travels, had to be limited Partners not-contributing due to funding issues Decide on which technology to work (or create a partner/technology table) Sharing of TSMC data needed? (used by NXP) What can be shared? Cross-references between Tasks/WP’s need to be identified Clarify project end date