1. IKI10230 Pengantar Organisasi Komputer Bab 10: Micro Architecture
Sumber: 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization, ed-5 3. Materi kuliah CS61C/2000 & CS152/1997, UCB
5 Mei 2004
L. Yohanes Stefanus Bobby Nazief
bahan kuliah:

2. Prosesor: Control & Datapath
Processor
(active)
Computer
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive)
(where
programs,
data
live when
running)
Devices
Input
Output
That is, any computer, no matter how primitive or advance, can be divided into five parts:
1. The input devices bring the data from the outside world into the computer.
2. These data are kept in the computer’s memory until ...
3. The datapath request and process them.
4. The operation of the datapath is controlled by the computer’s controller.
All the work done by the computer will NOT do us any good unless we can get the data back to the outside world.
5. Getting the data back to the outside world is the job of the output devices.
The most COMMON way to connect these 5 components together is to use a network of busses.

3. Organisasi Prosesor (Single-bus)Y Z
MDR
MAR PC
TEMP
R(n-1) R0 IR
Instruction
Decoder
ALU
Carry-in
Add
Sub
XOR
Address lines
Data lines
Control lines
Memory bus
ALU control lines
Control Unit
DatapathUnit

4. Legenda
PC: Program Counter
MAR: Memory Address Register
MDR: Memory Data Register
ALU: Arithmetic & Logic Unit
IR: Instruction Register
SP: Stack Pointer

5. Siklus Eksekusi Instruksi
Eksekusi instruksi yang ukurannya tetap
do {
1. IR  [[PC]] // Fetch instruksi
2. PC  [PC] + d // Tunjuk ke lokasi instruksi berikutnya
3. Eksekusi instruksi
} while (!stop)
Eksekusi instruksi yang ukurannya bervariasi
do { // Fetch instruksi
IR  [[PC]]
PC  [PC] + d
} while (!end-of-instruction)
Eksekusi instruksi

6. Operasi-operasi Dasar Dalam Eksekusi Instruksi
Pertukaran Data Antar-Register
Operasi Aritmatika & Logika di Datapath
Mengambil (fetching) Data dari Memori
Menyimpan (storing) Data ke Memori

7. Pertukaran Data Antar-Register
R1in
Instruksi:
MOV R4,R ; R4  [R1]
Langkah-langkah:
Enable output of R1 // setting R1out to 1
Enable input of R4 // setting R4in to 1 X R1 X
R1out
R4in X R4 X
R4out

8. Operasi Aritmatika dan LogikaY Z Ri
ALU A B X
Riin
Riout
Yin
Yout
Zin
Zout
Add
Instruksi:
ADD R1,R2 ; R1  [R1] + [R2]
Langkah-langkah:
R1out, Yin
R2out, Add, Zin
Zout, R1in

9. Mengambil Data dari MemoriY Z
MDR
MAR PC
TEMP R2 R1 IR
Instruction
Decoder
ALU
Carry-in
Add
Sub
XOR
Address lines
Data lines
Read
MFC
Instruksi:
MOV R2,[R1] ; R2  [[R1]]
Langkah-langkah:
MAR  [R1]
Read
Tunggu sinyal MFC // MFC = Memory Function Completed // Pada saat MFC aktif: // MDR  M[MAR]
R2  [MDR]

10. Menyimpan Data ke MemoriZ
MDR
MAR PC
TEMP R2 R1 IR
Instruction
Decoder
ALU
Carry-in
Add
Sub
XOR
Address lines
Data lines
Write
MFC
Instruksi:
MOV [R1],R2 ; [R1]  [R2]
Langkah-langkah:
MAR  [R1]
MDR  [R2], Write
Tunggu sinyal MFC // MFC = Memory Function Completed // Pada saat MFC aktif: // M[MAR]  MDR

11. Langkah-langkah Pengeksekusian Instruksi

12. Tahapan Eksekusi Instruksi
Add R1,[R3] ; R1  [R1] + [[R3]]
Langkah-langkah:
Fetch instruksi
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
Fetch operand (isi lokasi memori yg ditunjuk oleh R3)
R3out, MARin, Read
R1out, Yin, WMFC
Lakukan operasi penjumlahan
MDRout, Add, Zin
Simpan hasil penjumlahan di R1
Zout, R1in, End

13. 1. Fetch instruksi
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin Y Z
MDR
MAR PC
TEMP R3 R1 IR
Instruction
Decoder
ALU
Control lines
Address lines
Data lines
Add 1
[PC]+1
Carry-in

14. 2. Fetch operand R3out, MARin, Read R1out, Yin, WMFC ALU InstructionZ
MDR
MAR
PC=[PC]+1
TEMP R3 R1 IR
Instruction
Decoder
ALU
Address lines
Data lines

15. 3. Lakukan operasi penjumlahan
MDRout, Add, Zin
Y=[R1] Z
MDR=[[R3]]
MAR PC
TEMP R3 R1 IR
Instruction
Decoder
ALU
Address lines
Data lines
Add
Carry-in
Zin

16. 4. Simpan hasil penjumlahan
Zout, R1in, End
Y=R1
Z=[R1]+[[R3]]
MDR=M[R3]
MAR PC
TEMP R3 R1 IR
Instruction
Decoder
ALU
Address lines
Data lines

17. Tahapan Eksekusi “Branching”
Unconditional (JMP Loop)
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
PCout, Yin
Offset-field-of-IRout, Add, Zin // PC  [PC] + Offset
Zout, PCin, End
Conditional (contoh: JS Loop)
PCout, Yin , If SF=0 then End // take the branch?

18. MOV EAX,[EBX]

19. Tahapan Eksekusi Instruksi: MOV EAX,[EBX]
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EBXout, MARin, Read
WMFC
MDRout, EAXin, End Y Z
MDR
MAR PC
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Read
Address lines
PCout
Data lines
MARin
Clear Y
Add 1
Set Carry-in
[PC]+1
Zin

20. Tahapan Eksekusi Instruksi: MOV EAX,[EBX]
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EBXout, MARin, Read
WMFC
MDRout, EAXin, End Y
Z = [PC]+1
MDR
MAR PC
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
WMFC
Address lines
PCin
Data lines
Zout

21. Tahapan Eksekusi Instruksi: MOV EAX,[EBX]
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EBXout, MARin, Read
WMFC
MDRout, EAXin, End Y Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Address lines
IRin
Data lines
MDRout

22. Tahapan Eksekusi Instruksi: MOV EAX,[EBX]
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EBXout, MARin, Read
WMFC
MDRout, EAXin, End Y Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Read
Address lines
MARin
Data lines
EBXout

23. Tahapan Eksekusi Instruksi: MOV EAX,[EBX]
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EBXout, MARin, Read
WMFC
MDRout, EAXin, End Y Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
WMFC
Address lines
Data lines

24. Tahapan Eksekusi Instruksi: MOV EAX,[EBX]
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EBXout, MARin, Read
WMFC
MDRout, EAXin, End Y Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Address lines
Data lines
MDRout
EAXin

25. ADD EAX,EBX

26. Tahapan Eksekusi Instruksi: ADD EAX,EBX
ADD EAX,EBX ; EAX  [EAX] + [EBX]
Langkah-langkah:
Fetch instruksi
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
Fetch operand ke-1 (EAX)
EAXout, Yin
Fetch operand ke-2 (EBX) dan Lakukan operasi ALU
EBXout, Add, Zin
Simpan hasil penjumlahan di EAX
Zout, EAXin, End

27. Tahapan Eksekusi Instruksi: ADD EAX,EBX
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EAXout, Yin
EBXout, Add, Zin
Zout, EAXin, End Y Z
MDR
MAR PC
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Read
Address lines
PCout
Data lines
MARin
Clear Y
Add 1
Set Carry-in
[PC]+1
Zin

28. Tahapan Eksekusi Instruksi: ADD EAX,EBX
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EAXout, Yin
EBXout, Add, Zin
Zout, EAXin, End Y
Z = [PC]+1
MDR
MAR PC
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
WMFC
Address lines
PCin
Data lines
Zout

29. Tahapan Eksekusi Instruksi: ADD EAX,EBX
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EAXout, Yin
EBXout, Add, Zin
Zout, EAXin, End Y Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Address lines
IRin
Data lines
MDRout

30. Tahapan Eksekusi Instruksi: ADD EAX,EBX
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EAXout, Yin
EBXout, Add, Zin
Zout, EAXin, End Y Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Address lines
Data lines
Yin
EAXout

31. Tahapan Eksekusi Instruksi: ADD EAX,EBX
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EAXout, Yin
EBXout, Add, Zin
Zout, EAXin, End
Control lines
Instruction
Decoder
[PC]+1
Address lines
MAR IR
Data lines
MDR
EBX
EBXout
Y=EAX
EAX
Add
ALU
Zin Z
TEMP

32. Tahapan Eksekusi Instruksi: ADD EAX,EBX
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
Zout, PCin, WMFC
MDRout, IRin
EAXout, Yin
EBXout, Add, Zin
Zout, EAXin, End
Y=EAX Z
MDR
MAR
[PC]+1
TEMP
EAX
EBX IR
Instruction
Decoder
ALU
Control lines
Address lines
Data lines
EAXin
Zout

33. Peningkatan Kinerja Prosesor

34. Multiple-bus: salah satu cara peningkatan kinerja
MDR
MAR PC
TEMP
Register
File IR
Instruction
Decoder
ALU A B C
Data lines
Address lines
Memory Bus
Add R1,R2,R3 ;R1[R2]+[R3]

35. Bandingkan dengan Organisasi Single-busY Z
MDR
MAR PC
TEMP R3 R1 IR
Instruction
Decoder
ALU R2
Add R1,R2,R3 ;R1[R2]+[R3]

36. Beberapa Teknik Peningkatan Kinerja Prosesor Lainnya
Pre-fetching: instruksi berikutnya (i+1) di-fetch pada waktu pengeksekusian instruksi (i)
Perlu teknik “Branch Prediction”
Pipelining: eksekusi instruksi dipecah kedalam tahap-tahap yang dapat dilakukan secara “overlap”
Fetch Instruksi
Decode Instruksi
Baca Operand (dari register asal)
Lakukan Operasi
Tulis Hasil (ke register tujuan)
On-chip Cache: mempercepat akses data dari/ke memori

37. LAMPIRAN

38. Gating: Controlling Data Access from/to a Gate

39. Input & Output Gating Operasi Tulis Operasi Baca 1-bit bus Zin Q
1 bit line of common bus
Zin
Zout
3-state switch S R _Q Q
output: 1, 0, open-circuit
operasi tulis & baca dilakukan secara bergantian
memungkinkan peranti lain menggunakan bus
Operasi Tulis
Operasi Baca
1-bit bus Zin Q
X 0 Q
Zout Q output
0 X 3-state

40. Komponen-komponen Waktu Eksekusi

41. Komponen-komponen Waktu Eksekusi
Waktu Eksekusi Ditentukan Oleh:
Gate Delay
Waktu yang dibutuhkan output suatu gerbang logika berubah sesuai kondisi inputnya
Register’s Delay
Waktu yang dibutuhkan isi register berubah sesuai inputnya

42. Waktu Eksekusi: Gate Delay
When input 0  1, output 1  0 but NOT instantly
Output goes 1  0: output voltage goes from Vdd (5v) to 0v
When input 1  0, output 0  1 but NOT instantly
Output goes 0  1: output voltage goes from 0v to Vdd (5v)
Voltage does not like to change instantaneously
Voltage
Vout
1 => Vdd
Vin
You may ask yourself, why am I sitting here listening to all these transistors stuff while I am registered for a computer science class?
Well the reason is that we want to teach you to be a computer engineer, not a scientist.
As an engineer, you need to know the limitations God placed on the non-ideal world.
More specifically, let’s look at an inverter.
When the Inverter’s input goes from 0 to 1, the output of the inverter will go from 1 to 0, but not instantly. The voltage will drop from 5v to 0 gradually as shown in this plot.
Similarly, when the inverter’s input goes from 1 to 0, the output of the inverter will go from 0 to 1, but once again, NOT instantly. It will go from 0v to 5V gradually as shown here.
The bottom line here is that voltage, like any other physical quantities, does not like to change instantaneously.
+2 = 27 min. (Y:07)
Out In
0 => GND
Time

43. Waktu Eksekusi: Series Connection
Vdd
Vdd
Cout
Vout V1
Vin
Vout
Vin V1 G1 G2 G1 G2 C1
Voltage
Vdd V1
Vout
Vin
Vdd/2 d1 d2
GND
So far, we have look at the delay of one gate. But any system with only one gate is really not a very interesting system.
So let’s look at a more interesting system with two gates. For simplicity, I am representing the two gates as two inverters.
The total delay of this system will be the sum of the delay of these two gates.
More specifically, if we apply a step low to high transition at the input of the first gate, its output will go from high to low gradually and after a delay of d1, it will have fallen to Vdd/2.
At some point during this transition (points to V1 going H -> L), the PMOS transistor of the second inverter will start conducting and start driving the output toward 5v.
For simplicity, we have decided to measure the delay from the point when V1 and Vout reaches Vdd/2.
The last thing I want to point out on this slide is the capacitor between the two inverters.
You know, those EE guys are pretty smart sometimes. They draw two parallel lines at the transistor’s gate for a reason--to remind us there is some capacitance at the gate.
Therefore the capacitance value of this capacitor come from TWO sources. Capacitance of the wire connecting the gates. And the gate capacitance of the NMOS and PMOS transistors inside the second inverter.
+2 = 32 min. (Y:12)
Time
Total Propagation Delay = Sum of individual delays = d1 + d2
Capacitance C1 has two components:
Capacitance of the wire connecting the two gates
Input capacitance of the second inverter

44. Waktu Eksekusi: Register’s DelayQ
Don’t Care
Clk
Unknown
Setup
Hold
Clock-to-Q
Clk
Setup Time: Input must be stable BEFORE the trigger clock edge
Hold Time: Input must REMAIN stable after the trigger clock edge
Clock-to-Q time:
Output cannot change instantaneously at the trigger clock edge
So far we have been looking at combinational logic, let’s look at the timing characteristic of a storage element.
The storage element you will use is a D type flip-flop trigger on the negative clock edge.
In order for the data to latch into the flip flop correctly, the input must be stable slightly before the falling edge of the clock. This time is called the Setup time.
After the clock edge has arrived, the data must remain stable for a short amount of time AFTER the trigger clock edge. This is called the hold time.
The output cannot change instantaneously at the trigger clock edge. The time it takes for the output to change to its new value after the clock is called the Clock-to-Q time.
Similar to delay in logic gates, the Clock-to-Q time has two components:
(a) The internal Clock-to-Q time: the time it takes the output to change if output load is zero.
(b) And the load dependent Clock-to-Q time.
+2 = 50 min. (Y:30)

45. Waktu Eksekusi R2out, Add, Zin Turn-on time for 3-state driverY Z Ri
ALU A B X
Riin
Riout
Yin
Yout
Zin
Zout
Add
Turn-on time for 3-state driver
Transmission time
Propagation delay through ALU
Setup time
Hold time