1. Review for Exam 2 Using MUXs to implement logic
Using ROMs to implement logic
Timing Analysis
The internal structure of flip-flops
Flip-flop timings
Rising and falling edge triggered flip-flops
Counters and state machines
Generating next state equations from counter sequences.
Implementation using RS, D, T and JK flip-flops
Reading state sequence from timing diagrams
Determining next states from schematics
Moore vs. Mealy
Max frequency for a state machine
Verilog code

2. Implementing Logic Functions With Muxes
Z = A’B + BC’ I0 I1 I2 I3
4-to-1
MUX Z
for AB=00, Z=0
A B

3. Implementing Logic Functions With Muxes
Z = A’B + BC’ I0 I1 I2 I3 1
4-to-1
MUX Z
for AB=01, Z=1
A B

4. Implementing Logic Functions With Muxes
Z = A’B + BC’ I0 I1 I2 I3 1
4-to-1
MUX Z
for AB=11, Z=C’ C’
A B

5. Implementing Logic Functions With Muxes
Z = A’B + BC’ I0 I1 I2 I3 1
4-to-1
MUX Z C’
A B

6. Implementing Logic Functions With Muxes
An alternate method
Z = A’B + BC’
Z = C’ = 0
A=0 B=0
A=0 B=1
A=1 B=0
A=1 B=1 I0 I1 I2 I3
Z = C’ = 1 1
4-to-1
MUX Z
Z = C’ = 0 C’
Z = C’ = C’
A B

7. Using a ROM For Logic
Specify a truth table for a ROM which implements:
F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C

8. Using a ROM For Logic
Specify a truth table for a ROM which implements:
F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C

9. Using a ROM For Logic
Specify a truth table for a ROM which implements:
F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C

10. Using a ROM For Logic
Specify a truth table for a ROM which implements:
F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C

11. Timing Analysis A B AB E C D CD F
E+F X

12. Timing Analysis A B AB E C D CD F
E+F X

13. Timing Analysis A B AB E C D CD F
E+F X

14. Timing Analysis A B AB E C D CD F
E+F X

15. Timing Analysis A B AB E C D CD F
E+F X

16. Timing Analysis A B AB E C D CD F
E+F X

17. Timing Analysis A B AB E C D CD F
E+F X

18. The internal structure of flip-flopsD Q’ Q
GATE R S Q Q’
GATE GS GR D
CLK Q Q’
D-type Flip-Flop

19. The internal structure of flip-flops
CLK Q Q’ T
T-type Flip-Flop

20. The internal structure of flip-flopsJ Q Q’ K
CLK
JK-type Flip-Flop

21. Flip-flop timings Clock-to-QD Q Q’
CLK
tCLK  Q = tNOT + tAND + 2 x tNOR

22. Flip-flop timings Clock-to-Q
CLK D Q
tCLK Q
time

23. Flip-flop timings Setup timeD Q Q’
CLK
tsetup = tNOT + tAND + 2 x tNOR

24. Flip-flop timings Setup time
tsetup
CLK D Q
time

25. Flip-flop timings Hold timeQ Q’
thold = tNOT
CLK

26. Flip-flop timings Hold time
thold = tNOT
Clock edge
AND gate turns off, D can change
CLK D Q
time

27. Flip Flop Timing
thold
tsetup
CLK D Q
tCLK Q
time

28. Falling Edge Triggered DFF
Rising and falling edge triggered flip-flops D Q Q’
CLK
Falling Edge Triggered DFF

29. Rising Edge Triggered DFF
Rising and falling edge triggered flip-flops D Q Q’
CLK
Rising Edge Triggered DFF

30. Generating next state equations from counter sequences.
Desired count sequence = …
If current state = 00, next state = ?????
Implemented count sequence = …
N2 = Q2 Q1’ + Q1’ Q0
N1 = Q2
N0 = Q2’ Q0’ + Q1 Q0’

31. Implementation using RS, D, T and JK flip-flops

32. Reading state sequence from timing diagramsW X Y Z
WXYZ = 0010, 0110, 0011, 0101, 1100, 1000, 1001, 1101, 1110, 0010

33. Determining next states from schematicsQ2
Q2 Q1 Q0
Q1’
D Q Q2
Q1’
Initial state Q0
CLK
D Q Q1 Q2
CLK
Q2’
Q0’
D Q Q0 Q1
Q0’
CLK

34. Moore vs. Mealy

35. Max frequency for a state machine
Steps: 1. Determine the delay through the Flip Flops
2. Determine the delay through the IFL (max)
3. Add in setup time
4. Determine the smallest clock period possible
5. Max frequency =
clock period

36. Structural Verilog Code
and (output, input1, input2, ……);
nand (output, input1, input2, ……);
or (output, input1, input2, ……);
nor (output, input1, input2, ……);
not (output, input1);
buf (output, input1);
xor (output, input1, input2, ……);
xnor (output, input1, input2, ……);

37. Structural Verilog Code example
module mux21(q, sel, a, b);
input sel, a, b;
output q;
wire selbar, a1, a2;
not(selbar, sel);
and(a1, selbar, a);
and(a2, sel, b);
or(q, a1, a2);
endmodule a
sel a1 b a2 q
selbar

38. Dataflow Verilog Code

39. Dataflow Verilog Code example
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = (~sel & a) | (sel & b);
endmodule OR
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = sel?b:a;
endmodule

40. Verilog Code Heirarchy
module mux41(q, sel, a, b, c, d);
input[1:0] sel;
input a, b, c, d;
output q;
wire tmp1, tmp2;
mux21 M0(tmp1, sel[0], a, b);
mux21 M1(tmp2, sel[0], c, d);
mux21 M2(q, sel[1], tmp1, tmp2);
endmodule a b c d
mux41
sel 2 a b c d q
sel[0]
mux21
mux21
tmp1
tmp2
mux21
sel[1] q