1. 4-1 EE 319K Introduction to Embedded Systems Lecture 4: Arithmetic overflow, Branches, Control Structures, Abstraction & Refinement Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

2. 4-2 Agenda  Recap  Debugging  I/O oSwitch and LED interfacing  C Programming oRandom number generator, NOT gate in Keil  Outline  Arithmetic Overflow  Conditional Branches  Conditional and Iterative Statements oif, while, for (In assembly and C)  Abstraction & Refinement oDevice Driver Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

3. 4-3 Condition Codes  C set after an unsigned addition if the answer is wrong  C cleared after an unsigned subtract if the answer is wrong  V set after a signed addition or subtraction if the answer is wrong BitNameMeaning after add or sub Nnegativeresult is negative Zzeroresult is zero Voverflowsigned overflow Ccarryunsigned overflow Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

4. 4-4 96+64 224+64 8-bit unsigned number wheel C bit Cleared C bit Set  The carry bit, C, is set after an unsigned addition when the result is incorrect.  The carry bit, C, is clear after an unsigned subtraction when the result is incorrect. Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

5. 4-5 160-64 32-64 8-bit unsigned number wheel C bit SetC bit Cleared  The carry bit, C, is set after an unsigned addition when the result is incorrect.  The carry bit, C, is clear after an unsigned subtraction when the result is incorrect. Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

6. 4-6 Trick (unsigned) 1.Convert both numbers to unsigned 2.Perform addition or subtraction 3.Does the result fit as an unsigned? No -> addition C=1, subtraction C=0 Yes -> addition C=0, subtraction C=1 For example: 255 + 5 = 260, C = 1 and the actual answer is 260-256 = 4 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

7. 4-7 -32+64 96+64 8-bit signed number wheel V bit ClearedV bit Set  The overflow bit, V, is set after a signed addition or subtraction when the result is incorrect. Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

8. 4-8 32-64 -96-64 8-bit signed number wheel V bit Cleared V bit Set  The overflow bit, V, is normally set when we cross over from 127 to -128 while adding or cross over from -128 to 127 while subtracting. Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

9. 4-9 Trick (signed) 1.Convert both numbers to signed 2.Perform addition or subtraction 3.Does the result fit as a signed? No -> V=1 Yes -> V=0 8-bit Examples: 10 – 5 = 5, V=0 -100 – 100 = -200, V=1 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

10. 4-10 Addition Summary Let the 32-bit result R be the result of the 32-bit addition X+Y.  N bit is set  if unsigned result is above 2 31 -1 or  if signed result is negative.  N = R 31  Z bit is set if result is zero  V bit is set after a signed addition if result is incorrect   C bit is set after an unsigned addition if result is incorrect  Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

11. 4-11 Subtraction Summary Let the 32-bit result R be the result of the 32-bit subtraction X-Y.  N bit is set  if unsigned result is above 2 31 -1 or  if signed result is negative.  N = R 31  Z bit is set if result is zero  V bit is set after a signed subtraction if result is incorrect   C bit is clear after an unsigned subtraction if result is incorrect  Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

12. 4-12 Trick Question  Answer = 159  NZVC = 1010  When the subtraction (32 – 129) is performed in an 8-bit system what is the result and the status of the NZVC bits ? Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

13. 4-13 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari Unsigned Promotion  Promotion involves increasing the precision of the input numbers, and performing the operation at that higher precision  Then truncate the result back to the original precision Decimal 8-bit 32-bit 224 1110,0000 0000,0000,0000,0000,0000,0000,1110,0000 + 64 +0100,0000 +0000,0000,0000,0000,0000,0000,0100,0000 288 0010,0000 0000,0000,0000,0000,0000,0001,0010,0000

14. 4-14 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari Unsigned Ceiling and Floor

15. 4-15 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari Signed Promotion  To promote a signed number, we duplicate the sign bit Decimal 8-bit 32-bit -96 1010,0000 1111,1111,1111,1111,1111,1111,1010,0000 -64 -0100,0000 -0000,0000,0000,0000,0000,0000,0100,0000 -160 0110,0000 1111,1111,1111,1111,1111,1111,0110,0000

16. 4-16 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari Signed Ceiling and Floor

17. 4-17 Conditional Branch Instructions  Unsigned conditional branch  follow SUBS CMN or CMP BLO target ; Branch if unsigned less than (if C=0, same as BCC) BLS target ; Branch if unsigned less than or equal to (if C=0 or Z=1) BHS target ; Branch if unsigned greater than or equal to (if C=1, same as BCS) BHI target ; Branch if unsigned greater than (if C=1 and Z=0) CMP R0,R1 BLO R0<R1 target Next instruction R0≥R1 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

18. 4-18 Conditional Branch Instructions  Signed conditional branch  follow SUBS CMN or CMP BLT target ; if signed less than(if (~N&V | N&~V)=1, i.e. if N≠V) BGE target ; if signed greater than or equal to (if (~N&V | N&~V)=0, i.e. if N=V) BGT target ; if signed greater than (if (Z | ~N&V | N&~V)=0, i.e. if Z=0 and N=V) BLE target ; if signed less than or equal to (if (Z | ~N&V | N&~V)=1, i.e. if Z=1 or N≠V) CMP R0,R1 BLT R0<R1 target Next instruction R0≥R1 Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

19. 4-19 Equality Test Program 5.8. Conditional structures that test for equality. Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

20. 4-20 Unsigned Conditional Structures Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari Program 5.9. Unsigned conditional structures.

21. 4-21 Signed Conditional Structures Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari Program 5.11. Signed conditional structures.

22. 4-22 If-then-else Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

23. 4-23 While Loops LDR R4, =G1 ; R4 -> G1 LDR R5, =G2 ; R5 -> G2 loop LDR R0, [R5] ; R0 = G2 LDR R1, [R4] ; R1 = G1 CMP R0, R1 ; is G2 <= G1? BLS next ; if so, skip to next BL Body ; body of the loop B loop next uint32_t G1,G2; while(G2 > G1){ Body(); } Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

24. 4-24 For Loops Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

25. 4-25 For Loops MOV R4, #0 ; R4 = 0 loop CMP R4, #100 ; index >= 100? BHS done ; if so, skip to done BL Process ; process function* ADD R4, R4, #1 ; R4 = R4 + 1 B loop done for(i=0; i<100; i++){ Process(); } MOV R4, #100 ; R4 = 0 loop BL Process ; process function SUBS R4, R4, #1 ; R4 = R4 - 1 BNE loop done for(i=100; i!=0; i--){ Process(); } Count up Count down Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

26. 4-26 System Design  What does being in a state mean?  List state parameters  What is the starting state of the system?  Define the initial state  What information do we need to collect?  List the input data  What information do we need to generate?  List the output data  How do we move from one state to another?  Actions we could do  What is the desired ending state?  Define the ultimate goal Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

27. 4-27 System Design  Successive Refinement  Stepwise Refinement  Systematic Decomposition Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

28. 4-28 System Design  Start with a task and decompose the task into a set of simpler subtasks  Subtasks are decomposed into even simpler sub-subtasks  Each subtask is simpler than the task itself  Make design decisions  document decisions and subtask requirements  Ultimately, subtask is so simple, it can be converted to software Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

29. 4-29 System Design  Four building blocks:  “do A then do B” → sequential  “do A and B in either order” → sequential (parallel)  “if A, then do B” → conditional  “for each A, do B” → iterative  “do A until B” → iterative  “repeat A over & over forever” → iterative (condition always true)  “on external event do B” → interrupt  “every t msec do B” → interrupt Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

30. 4-30 Successive Refinement Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

31. 4-31 Successive Refinement Successive refinement example for iterative approach Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

32. 4-32 Abstraction - Device Driver Abstraction allows us to modularize our code and give us the option to expose what we want users to see and hide what we don’t want them to see. A Device Driver is a good example where abstraction is used to expose public routines that we want users of the driver to call and use private routines to hide driver internals from the user (more on private routines later) Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari LED Driver (PE0) LED_Init LED_Off LED_On LED_Toggle A user simply has to know what a routine expects and what it returns in order to call it (calling convention). Internals do not matter to caller

33. 4-33 Port E LED Abstraction PE0 EQU 0x4005C004 ;bit-specific address Port E bit 0 LED_Init LDR R1, =SYSCTL_RCGCGPIO_R ; R1 -> SYSCTL_RCGCGPIO_R LDR R0, [R1] ; previous value ORR R0, R0, #0x00000010 ; activate clock for Port E STR R0, [R1] NOP NOP ; allow time to finish activating LDR R1, =GPIO_PORTE_DIR_R ; R1 -> GPIO_PORTE_DIR_R LDR R0, [R1] ; previous value ORR R0, R0, #0x01 ; PE0 output STR R0, [R1] ; set direction register LDR R1, =GPIO_PORTE_AFSEL_R ; R1 -> GPIO_PORTE_AFSEL_R LDR R0, [R1] ; previous value BIC R0, R0, #0x01 ; disable alt funct STR R0, [R1] ; set alternate function register LDR R1, =GPIO_PORTE_DEN_R ; R1 -> GPIO_PORTE_DEN_R LDR R0, [R1] ; previous value ORR R0, R0, #0x01 ; enable PE0 digital port STR R0, [R1] ; set digital enable register BX LR Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip). Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari

34. 4-34 Port E LED Abstraction LED_Off LDR R1, =PE0 ; R1 is 0x4005C004 MOV R0, #0 STR R0, [R1] ; affect just PE0 BX LR LED_On LDR R1, =PE0 ; R1 is 0x4005C004 MOV R0, #1 STR R0, [R1] ; affect just PE0 BX LR LED_Toggle LDR R1, =PE0 ; R1 is 0x4005C004 LDR R0, [R1] ; previous value EOR R0, R0, #1 ; flip bit 0 STR R0, [R1] ; affect just PE0 BX LR Program 4.3. Software interface for an LED on PE0 (SSR_xxx.zip). Bard, Erez, Gerstlauer, Valvano, Yerraballi, Telang, Janapa Reddi, Tiwari