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Computer Architecture: A Constructive Approach Six Stage Pipeline/Bypassing Joel Emer Computer Science & Artificial Intelligence Lab. Massachusetts Institute.

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Presentation on theme: "Computer Architecture: A Constructive Approach Six Stage Pipeline/Bypassing Joel Emer Computer Science & Artificial Intelligence Lab. Massachusetts Institute."— Presentation transcript:

1 Computer Architecture: A Constructive Approach Six Stage Pipeline/Bypassing Joel Emer Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology March 14, 2012 http://csg.csail.mit.edu/6.S078 L11-1

2 Three-Cycle SMIPS: Analysis Fetch Decode/RegRead/ Execute/Memory Fetch Does Fetch or DRXM depend on Writeback? March 14, 2012 http://csg.csail.mit.edu/6.S078 Yes, for register values pc ir Writeback mr Writeback wr L11-2

3 Stall calculation March 14, 2012 http://csg.csail.mit.edu/6.S078 Stall calculation WB Stall Reg WB Feedback wbStall L11-3

4 Data dependence waterfall March 14, 2012 http://csg.csail.mit.edu/6.S078 From whiteboard L11-4

5 Types of Data Hazards March 14, 2012 http://csg.csail.mit.edu/6.S078 Data-dependence r 3  (r 1 ) op (r 2 ) Read-after-Write r 5  (r 3 ) op (r 4 )(RAW) hazard Consider executing a sequence of instructions like: r k (r i ) op (r j ) Anti-dependence r 3  (r 1 ) op (r 2 ) Write-after-Read r 1  (r 4 ) op (r 5 )(WAR) hazard Output-dependence r 3  (r 1 ) op (r 2 ) Write-after-Write r 3  (r 6 ) op (r 7 ) (WAW) hazard L11-5

6 March 14, 2012 http://csg.csail.mit.edu/6.S078 Detecting Data Hazards Range and Domain of instruction i R(i) = Registers (or other storage) modified by instruction i D(i) = Registers (or other storage) read by instruction i Suppose instruction j follows instruction i in the program order. Executing instruction j before the effect of instruction i has taken place can cause a RAW hazard if R(i)  D(j)  WAR hazard if D(i)  R(j)  WAW hazard if R(i)  R(j)  L11-6

7 March 14, 2012 http://csg.csail.mit.edu/6.S078 Register vs. Memory Data Dependence Data hazards due to register operands can be determined at the decode stage but Data hazards due to memory operands can be determined only after computing the effective address storeM[(r1) + disp1]  (r2) loadr3  M[(r4) + disp2] Does (r1 + disp1) = (r4 + disp2) ? L11-7

8 March 14, 2012 http://csg.csail.mit.edu/6.S078 Data Hazards: An Example I 1 DIVDf6, f6,f4 I 2 LDf2,45(r3) I 3 MULTDf0,f2,f4 I 4 DIVDf8,f6,f2 I 5 SUBDf10,f0,f6 I 6 ADDDf6,f8,f2 RAW Hazards WAR Hazards WAW Hazards L11-8

9 Scoreboard Add a scoreboard of registers in use: Set bit for each register to be updated Clear bit when a register is updated Stall if bit for a register needed is set March 14, 2012 http://csg.csail.mit.edu/6.S078 R31 R0 Register#(Bit#(32)) scoreboard <- mkReg(0); L11-9

10 SMIPs Pipeline Analysis StageTclock > Six stage FetchtMtM Decodet DEC Register Readt RF Executet ALU MemorytMtM Writebackt WB March 14, 2012 http://csg.csail.mit.edu/6.S078L11-10

11 Six Stage Pipeline March 14, 2012 http://csg.csail.mit.edu/6.S078 F Fetch D Decode R Reg Read X Execute M Memory W Write- back Where do we need feedback? X to F and W to R L11-11

12 Six-Stage State module mkProc(Proc); Reg#(Addr) fetchPc <- mkRegU; RFile rf <- mkRFile; Memory mem <- mkMemory; FIFO#(FBundle) fr <- mkFIFO; FIFO#(DecBundle) dr <- mkFIFO; FIFO#(RegBundle) rr <- mkFIFO; FIFO#(EBundle) xr <- mkFIFO; FIFO#(WBundle) mr <- mkFIFO; FIFOF#(Addr) nextPc <- mkFIFOF; FIFOF#(Rindx) wbRind <- mkFIFOF; // and internal control state… March 14, 2012 http://csg.csail.mit.edu/6.S078L11-12

13 Six-Stage Fetch rule doFetch; Addr pc = ?; Bool epoch = fetchEpoch; if (nextPc.notEmpty) begin pc = nextPc.first; epoch = !fetchEpoch; nextPc.deq; end else pc = fetchPc + 4; fetchPc <= pc; fetchEpoch <= epoch; let instResp <- mem.op(MemReq{op:Ld, addr:pc, data:?}); fr.enq(FBundle{pc:pc,epoch:epoch,InstResp:instResp}); endrule March 14, 2012 http://csg.csail.mit.edu/6.S078L11-13

14 Six-Stage Decode rule doDecode; let fetchInst = fr.first; let pcPlus4 = fetchInst.predpc + 4; let decInst = decode(fetchInst.instResp, pcPlus4); decInst.epoch = fetchInst.epoch; dr.enq(decInst); fr.deq; endrule March 14, 2012 http://csg.csail.mit.edu/6.S078L11-14

15 Register Read Stage March 14, 2012 http://csg.csail.mit.edu/6.S078 R Reg Read Read regs RF W RF must be available to ReadSrcs and Writeback! D Decode L11-15

16 Register Read Module typedef struct { Data: src1; Data: src2 } Sources; module mkRegRead#(RFile rf)(RegRead); Reg#(Bool) scoreboardReg <- mkReg(False); Dwire#(Bool) scoreboard <-mkDwire(scoreboardReg); rule updateScoreboard; scoreboardReg <= scoreboard; endrule method Maybe#(Sources) readRegs(DecodeInst decInst); let src1 = rf.rd1(decInst.op1); let src2 = … if (scoreboardReg) return tagged Invalid; else return tagged Valid Sources{src1:src1,…}; endmethod March 14, 2012 http://csg.csail.mit.edu/6.S078L11-16

17 Register Read Module typedef struct { Data: src1; Data: src2 } Sources; module mkRegRead#(RFile rf)(RegRead); Reg#(Bool) scoreboardReg <- mkReg(False); method Maybe#(Sources) readRegs(DecodeInst decInst); let src1 = rf.rd1(decInst.op1); let src2 = … if (scoreboardReg) return tagged Invalid; else return tagged Valid Sources{src1:src1,…}; endmethod March 14, 2012 http://csg.csail.mit.edu/6.S078 To use need to instantiate with: let readreg <- mkReadReg(rf); L11-17

18 Six-Stage Register Read (cont) RWire#(Bool) next_available <-mkRWire; RWire#(Bool) next_unavailable <- mkRWire; method markAvailable(); next_available.wset(False); endmethod method markUnavailable(); next_unavailable.wset(True); endmethod rule updateScoreboard; if (next_unavailable matches tagged Valid.ua) scoreboardReg <= True; else if (next_available matches tagged Valid.a) scoreboardReg <= False; endrule endmodule March 14, 2012 http://csg.csail.mit.edu/6.S078L11-18

19 Six-Stage Register Read rule doRegRead; if (wbRind.notEmpty) begin readreg.markAvailable(); wbRind.deq; end let decInst = dr.first(); if (execEpoch != decInst.epoch) begin readreg.markAvailable(); dr.deq() end; else begin maybeSources = readregs.readRegs(decInst); if (maybeSources match tagged Valid.sources) begin if (writesreg(decInst)) rr.markUnavailable(); rr.enq(RegBundle{decodebundle: decInst, src1: srouces.src1, src2: sources.src2}); dr.deq(); end endrule March 14, 2012 http://csg.csail.mit.edu/6.S078 Better scoreboard will need register index! L11-19

20 Six-Stage Execute rule doExecute; let decInst = rr.first.decodebundle; let epochChange = (decInst.epoch != execEpoch); let src1 = rr.first.src1; let src2 =... if (! epochChange) begin let execInst = exec.exec(decInst, src1, src2); if (execInst.cond) begin nextPc.enq(execInst.addr); execEpoch <= !execEpoch; end xr.enq(execInst); end rr.deq(); endrule March 14, 2012 http://csg.csail.mit.edu/6.S078L11-20

21 Six-Stage Memory rule doMemory; let execInst = xr.first; if (execInst.itype==Ld || execInst.itype==St) begin execInst.data <- mem(MemReq{ op:execInst.itype==Ld ? Ld : St, addr:execInst.addr, data:execInst.data}); end mr.enq(WBBundle{itype:execInst.itype, rdst:execInst.rdst, data:execInst.data}); xr.deq(); endrule March 14, 2012 http://csg.csail.mit.edu/6.S078L11-21

22 Six-Stage Writeback rule doWriteBack; wbRind.enq(mr.first.rdst); rf.wr(mr.first.rdst, mr.first.data); mr.deq; endrule March 14, 2012 http://csg.csail.mit.edu/6.S078L11-22

23 Six Stage Waterfall March 14, 2012 http://csg.csail.mit.edu/6.S078 From whiteboard L11-23

24 Bypass March 14, 2012 http://csg.csail.mit.edu/6.S078 RegRead Execute rr If scoreboard says register is not available then RegRead needs to stall, unless it sees what it needs on the bypass line…. What does RegRead need to do? L11-24

25 Bypass Network March 14, 2012 http://csg.csail.mit.edu/6.S078 typedef struct { Rindx regnum; Data value;} BypassValue; Module mkBypass(BypassNetwork) Rwire#(BypassValue) bypass; method produceBypass(Rindx regnum, Data value); bypass = BypassValue{regname: regnum, value:value}; endmethod method Maybe#(Data) consumeBypass(Rindx regnum); if (bypass matches tagged Valid.b && b.regnum == regnum) return tagged Valid b.value; else return tagged Invalid; endmethod endmodule Real network will have many sources. How are they ordered? From earlier stages to later L11-25

26 Register Read (with bypass) module mkRegRead#(RFile rf, BypassNetwork bypass)(RegRead); method Maybe#(Sources) readRegs(DecodeInst decInst); let src1 = rf.rd1(decInst.op1); let src2 = … if (!scoreboardReg) return tagged Valid Sources{src1:src1,…}; else begin let b1 = bypass.consumebypass(decInst.op1); let b2 = if (b1 matches tagged Valid.v1 && b2 matches…) return tagged Valid Sources{src1:v1.value …); else return tagged Invalid; end endmethod March 14, 2012 http://csg.csail.mit.edu/6.S078L11-26

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