1. CML CML CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

2. CML CMLQuestion What is the difference between a calculator and a computer A desk calculator is a “fixed program computer”. –Cannot change the program of such a machine –You have to re-wire, re-structure, or even re-design the machine Computers are “stored program computers” –The program is a software –You can feed in new set of instructions and you have a completely different functionality BIG IDEA – Stored Program Concept Chief Instrument of change –Instruction Set Architecture

3. CML CML Stored Program Concept Everything is represented and stored as a “bit sequence” –The program, compiler, editor, Operating System, input interface, GUI, etc… Provides amazing degree of flexibility –Computers can be used to simulate “anything that is simulatable” –Compare this with a calculator

4. CML CMLAnnouncements Quiz 1 on Thursday, Sept 10, 2009 –Open Book, Open notes, open internet –Chapter 2, (2.1-2.6) Arithmetic, Load Store and Branch instructions –Just no function calls Project 0 –Start exploring MARS MIPS simulator Install it on your machine Write some assembly language programs, e.g., add two numbers –DO NOT SUBMIT Project 1 –Will be online on Thursday –About writing some assembly language programs –Due in 1 week, end of Wednesday

5. CML CML What you need to know So far – –Should be able to write assembly programs for Arithmetic operations Given memory state, and some load store operations, you should be able to tell what is the final state of the memory Convert assembly instructions to binary forms –R and I format instructions Today – –Should be able to write assembly programs for Control flow - Branches, loops Except function calls

6. CML CML  High-level language program (in C) swap (int v[], int k)...  Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Below the Program C - Compiler Assembler

7. CML MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1

8. CML CML MIPS R3000 ISA Instruction Categories –Arithmetic –Load/Store –Jump and Branch –Floating Point coprocessor –Memory Management –Special R0 - R31 PC HI LO OP rsrt rdsafunct rs rtimmediate jump target Registers R Format I Format 6 bits5 bits 6 bits 3 Instruction Formats: all 32 bits wide 6 bits5 bits 6 bits

9. CML CML 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hardware) 0$zero constant 0 (Hardware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Naming Convention for Registers

10. CML CML 32 registers ($zero - $ra) MIPS Organization so far Arithmetic instructions – to/from the register file Load/store instructions - to/from memory read data 32 5 5 5 src1 addr src2 addr dst addr write data 32 bits 32 Processor Memory 32 bits 2 30 words read/write addr write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 data src2 data 32 ALU 0123 7654 byte address (big Endian)

11. CML CML Which end do you break your egg? Gulliver’s Travel –Lilliput: Sharp-end(Little-endian) –Blefuscu: Rounded-end(Big-endian) Suppose, we have these two values in registers We store these values in memory 1111 1111 0000 0000 1111 0000 0000 1111 0000 0000 1111 1111 0000 1111 1111 0000 $s1 = $s2 = lw $s1 4($t0) lw $s2 8($t0) $t0= 0x4080

12. CML CML What does the memory look like? 4/15/201512 1111 0000 0 1 Increasing Address 4084 4085 4086 4087 1111 0000 0000 1111 $s1 = $s2 = 1111 0000 4088 4089 408a 408b 1111 0000 0000 1111... 1111 0000 0 1 Increasing Address 4084 4085 4086 4087 1111 0000 0000 1111 1111 0000 4088 4089 408a 408b 1111 0000 0000 1111... $t0= 0x4080 lw $s1 4($t0) lw $s2 8($t0) 1111 0000 1111 00000000 1111 1111 0000 1111 00000000 1111

13. CML CML Memory Addressing What is the word at address 4080? 4/15/201513 Memory Address 4080 4084 4088 1111 1111 0000 0000 1111 0000 0000 1111 1111 0000 0000 1111 1111 1111 0000 0000 0000 0000 1111 0000 0000 1111 1111 1111 1111 1111 0000 0000 1111 0000 0000 1111 What is the byte at address 4086? Memory Address 4080 4084 4088 1111 1111 0000 0000 1111 0000 0000 1111 1111 0000 0000 1111 1111 1111 0000 0000 0000 0000 1111 0000 0000 1111 1111 1111 0123 4567 891011 3210 7654 1098

14. CML CML Memory Addressing What is the word at address 4080? 4/15/201514 Little Endian Memory Address 4080 4084 4088 1111 1111 0000 0000 1111 0000 0000 1111 1111 0000 0000 1111 1111 1111 0000 0000 0000 0000 1111 0000 0000 1111 1111 1111 1111 1111 0000 0000 1111 0000 0000 1111 What is the byte at address 4086? Big Endian Memory Address 4080 4084 4088 1111 1111 0000 0000 1111 0000 0000 1111 1111 0000 0000 1111 1111 1111 0000 0000 0000 0000 1111 0000 0000 1111 1111 1111 0123 4567 891011 3210 7654 1098 1111 0000 1111 Leftmost byte is word address e.g., Motorola 68k, MIPS, Sparc, HP PA Rightmost byte is word address e.g., Intel 80x86, DEC Vax, DEC Alpha

15. CML CML Endian-ness and Alignment Big Endian: leftmost byte is at word address Little Endian: rightmost byte is at word address 4/15/201515 msblsb 3 2 1 0 little endian byte 0 0 1 2 3 big endian byte 0 Alignment restriction: requires that objects fall on address that is multiple of their size. Aligned Not Aligned 0 1 2 3

16. CML CML Loading and Storing Bytes MIPS provides special instructions to move bytes lb $t0, 1($s3) #load byte from memory sb $t0, 6($s3) #store byte to memory What 8 bits get loaded and stored? –load byte places the byte from memory in the rightmost 8 bits of the destination register what happens to the other bits in the register? –store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory 4/15/201516 op rs rt 16 bit number

17. CML CML Example of Loading and Storing Bytes Given following code sequence and memory state (contents are given in hexadecimal), what is the state of the memory after executing the code? add$s3, $zero, $zero lb$t0, 1($s3) sb$t0, 6($s3) 4/15/201517 Memory 0 0 9 0 1 2 A 0 Data Word Address (Decimal) 0 4 8 12 16 20 24 F F F F 0 1 0 0 0 4 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0  What value is left in $t0?  What if the machine was little Endian? $t0 = 0x00000090 mem(4) = 0xFFFF90FF mem(4) = 0xFF12FFFF $t0 = 0x00000012

18. CML CML Instructions for Making Decisions Decision making instructions –alter the control flow –i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $s0, $s1, Label#go to Label if $s0  $s1 beq $s0, $s1, Label#go to Label if $s0=$s1 Example: if (i==j) h = i + j; bne $s0, $s1, Lab1 add $s3, $s0, $s1 Lab1:...

19. CML CML op rs rt 16 bit number Assembling Branches Instructions: bne $s0, $s1, Label#go to Label if $s0  $s1 beq $s0, $s1, Label#go to Label if $s0=$s1 Machine Formats: I format 5 16 17 ???? 4 16 17 ???? How is the branch destination address specified?

20. CML CML bne $s0,$s1,Lab1 add $s3,$s0,$s1 Specifying Branch Destinations Could use a register (like lw and sw) and add to it the 16-bit offset –which register? Instruction Address Register –PC = program counter its use is automatically implied by instruction PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction –limits the branch distance to -2 15 to +2 15 -1 instructions from the (instruction after the) branch instruction, but most branches are local anyway (principle of locality)... Lab1: PC  Could specify the memory address –But that would require 32 bit field

21. CML CML Disassembling Branch Destinations The contents of the updated PC (PC+4) is added to the low order 16 bits of the branch instruction which is converted into a 32 bit value by –concatenated two low-order zeros to create an 18 bit number –sign-extending those 18 bits The result is written into the PC if the branch condition is true prior to the next Fetch cycle PC Add 32 offset 16 32 00 sign-extend from the low order 16 bits of the branch instruction branch dst address ? Add 4 32

22. CML CML op rs rt 16 bit offset 5 16 17 Assembling Branches Example Assembly code bne $s0, $s1, Lab1 add $s3, $s0, $s1 Lab1:... Machine Format of bne : I format 1 Remember –After the bne instruction is fetched, the PC is updated to address the add instruction (PC = PC + 4). –Two low-order zeros are concatenated to the offset number and that value sign-extended is added to the (updated) PC

23. CML CML Another Instruction for Changing Flow MIPS also has an unconditional branch instruction or jump instruction: j label#go to label Example: if (i!=j) h=i+j; else h=i-j; beq$s0, $s1, Lab1 add$s3, $s0, $s1 jLab2 Lab1:sub$s3, $s0, $s1 Lab2:...

24. CML CML op 26-bit address Assembling Jumps Instruction: j label#go to label Machine Format: How is the jump destination address specified? –As an absolute address formed by concatenating the upper 4 bits of the current PC (now PC+4) to the 26-bit address and concatenating 00 as the 2 low-order bits J format 2 ????

25. CML CML Disassembling Jump Destinations The low order 26 bits of the jump instruction is converted into a 32 bit jump instruction destination address by –concatenating two low-order zeros to create an 28 bit (word) address –concatenating the upper 4 bits of the current PC (now PC+4) to create a 32 bit instruction address that is placed into the PC prior to the next Fetch cycle PC 4 32 26 32 00 from the low order 26 bits of the jump instruction

26. CML CML Assembling Branches and Jumps Assemble the MIPS machine code (in decimal is fine) for the following code sequence. Assume that the address of the beq instruction is 0x00400020 (hex address) beq$s0, $s1, Lab1 add$s3, $s0, $s1 jLab2 Lab1:sub$s3, $s0, $s1 Lab2:... 0x00400020416172 0x0040002401617190 32 0x0040002820000 0100 0... 0 0011 00 2 0x0040002c01617190 34 0x00400030... jmp dst = (0x0) 0x040003 00 2 (00 2 ) = 0x00400030

27. CML CML Compiling While Loops Compile the assembly code for the C while loop where i is in $s0, j is in $s1, and k is in $s2 while (i!=k) i=i+j; Loop:beq$s0, $s2, Exit add$s0, $s0, $s1 jLoop Exit:...

28. CML CML op rs rt rd funct 0 16 17 8 0 42 = 0x2a More Instructions for Making Decisions We have beq, bne, but what about branch-if-less-than? New instruction: slt $t0, $s0, $s1 # if $s0 < $s1 # then # $t0 = 1 # else # $t0 = 0 Machine format: 2

29. CML CML Other Branch Instructions Can use slt, beq, bne, and the fixed value of 0 in register $zero to create all relative conditions –less than blt $s1, $s2, Label –less than or equal to ble $s1, $s2, Label –greater than bgt $s1, $s2, Label –great than or equal to bge $s1, $s2, Label Example - slt $t0, $s1, $s2#$t0 set to 1 if bne $t0, $zero, Label# $s1 < $s2

30. CML CML op rs funct 0 9 0 0 0 8 = 0x08 Another Instruction for Changing Flow Most higher level languages have case or switch statements allowing the code to select one of many alternatives depending on a single value. Instruction: jr $t1#go to address in $t1 Machine format: 2

31. CML CML Compiling a Case (Switch) Statement switch (k) { case 0: h=i+j; break; /*k=0*/ case 1: h=i+h; break; /*k=1*/ case 2: h=i-j; break; /*k=2*/ Assuming three sequential words in memory starting at the address in $t4 have the addresses of the labels L0, L1, and L2 and k is in $s2 add$t1, $s2, $s2#$t1 = 2*k add$t1, $t1, $t1#$t1 = 4*k add$t1, $t1, $t4#$t1 = addr of JT[k] lw$t0, 0($t1)#$t0 = JT[k] jr$t0#jump based on $t0 L0:add$s3, $s0, $s1#k=0 so h=i+j jExit L1:add$s3, $s0, $s3#k=1 so h=i+h jExit L2:sub$s3, $s0, $s1#k=2 so h=i-j Exit:... $t4  L0 L1 L2 Memory

32. CML MIPS Instructions, so far CategoryInstrOp CodeExampleMeaning Arithmetic (R format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1 load byte32lb $s1, 101($s2)$s1 = Memory($s2+101) store byte40sb $s1, 101($s2)Memory($s2+101) = $s1 Cond. Branch br on equal4beq $s1, $s2, Lif ($s1==$s2) go to L br on not equal5bne $s1, $s2, Lif ($s1 !=$s2) go to L set on less than0 and 42slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0 Uncond. Jump jump2j 2500go to 10000 jump register0 and 8jr $t1go to $t1

33. CML CML 32 read data 32 5 5 5 1 5 MIPS Organization Processor Memory 32 bits 2 30 words read/write addr write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers ($zero - $ra) 32 PC ALU023 764 byte address (big Endian) Fetch PC = PC+4 DecodeExec Add 4 br offset

34. CML CML MIPS R3000 ISA Instruction Categories –Arithmetic –Load/Store –Jump and Branch –Floating Point coprocessor –Memory Management –Special R0 - R31 PC HI LO OP rsrt rdsafunct rs rtimmediate 26-bit jump target Registers R Format I Format 6 bits5 bits 6 bits 3 Instruction Formats: all 32 bits wide 6 bits5 bits 16 bits J Format 6 bits26 bits

35. CML CML Yoda says… Luke: What's in there? Yoda: Only what you take with you