1. 7/6/01A. Sukhanov

2. 01/10/03A. Sukhanov2 L0 Logic CC Veto L0 Heartbeat Pedestal TOF Cal PNPP Wide R R R R R R R R L0 R R R 26 ns TML0 N N 1 R 55 CO.1 G12.3 C2.16 CI.15 TOF ADC Gate CAT ADC Gate 108206 C2.13 FI G9.B 45268 4 ns 60210 R N Connected to a register Connected to a scaler Twisted pair dECL lines All times are relative to PNPP wide Trig TDC C3.16 Busy from L1 L1C0.15 L0 to L1 L1CI.0 d 114 G12.10 CO.0 Time=0 2520 in the case of FC 2 ms normal C2.12 C2.10 C2.11 C2.09 Si Cosmic CO.2 Paddle ADC Gate ADC 6 L0Pulse G12.1 TOF+PaddlesTDC Start CAT ICAS G12.4 ZCAL ADC Gate ADC 7 R N ZCAL C2.14 74 G6AG6CG6BG11CG11B G12.5 ZGate ZExclGate R d Exclusive ZCAL trigger 43? 164? D C Non ZCAL trigger D C CO.4 CO.3 Changes: 8/28/00 front of the ZCAL ADC made earlier by 16 ns 11/02/00 TOFrig applied to G11C bypassing 40ns delay to gain 40 ns for TOF cosmic 11/13/00 Drawing error, swapped C2.10 C2-11 7/04/01 G12 input changes to fit the flat cable arrangement 7/05/01 Paddle ADC Gate G12.3-G6B cable delay changed from 48 to 16ns. G6B changed to 140ns 7/06/01 Paddle ADC Gate G12.3-G6B cable delay changed from 16 to 4ns. G6B changed to 152ns 11/13/02 Paddle ADC Gate G6B is taken from G12.2 not G12.6. 11/14/02 Added MPI, prescalers T[0:3] 01/10/03 Added PCAL gates 4 ns D C 64 ns ZCAL+PaddlesTDC Start TDC 4+5 G12.6 CO.5 44 124 288 408 220us 1800us Busy from FB. NIMOUT 0 G12.2 44 56 1/N RN MPI Measured Pause Interval for pileup control ! D C G5.10 G5.09 PCAL cosmic gate PCAL main gate CO.8 CO.9 G5.09 L0 FanOut CO.10 CO.11

3. 8/26/01A. Sukhanov3 1/N L0 from G11B Pn*Pp(2) from A8B ZTrig from D7C Fast Clear TML1 L1 to DAQ (EMM.CI.0) Veto to L0 R R R R R R R R R N N RN L1 logic PN*PP narrow L0 PN*PP wide Fast Clear L1 D 1 C D C D C Event Accepted L1 to EMS Silicon (CI.0) 1000 1060 CO.0 R N Connected to a register Connected to a scaler Twisted pair dECL lines CO.2 G12.13 CO.15 Busy L1 Trig TDC (C3.8) CO.1 L1 55 1/N Prescaler Note. Before 07/12/00 the G11A output has been at 180 ns Changes: 5/29/01. Drawing error. G11B to G11A 7/4/01. G12.13, CO.2 G11A 5000526 0 1 3 2 4 5 6 7 Centrality from A12B Heartbeat from C10C Pn*Pp Narrow from A2B 2520114 Vtx from A10B CVtx from A12A 0.0-3 0.4-7 0.8-11 0.12-15 3.0-3 3.4-7 3.8-11 3.12-15

4. 04/17/04A. Sukhanov4 EMM 15) Token014) Token113) Token212) Token311) Token410) Token509) Token608) Token707) TokStrobe05) CO504) Trig Pulse03) SiL202) SiL100) Busy16) GND - Cout + + Cin - 01) HShk06) HShk 01) 02) 03) 04) 05) 06) + G5 - Red Orange Yellow Green Blue Purple SiL2, SiL2 G8.2:3 BusyEMM. G9.3 SiL1, SiL1 G8.0:1 07) To VMERoc and FastBus 16 15 14 13 12 Busy L0 Busy L1 Busy Si Busy FBROC Busy VROC Busy Forced Busy PHTMS 11 10 9 8 7 6 5 4 3 2 1 0 CI[15] SynCal MDCL2 CI[14] CI[13] CI[12] CI[11] CI[10] Trig0 GND G10 Busy L0 Busy L1 Busy Si Busy FBROC Busy VROC Busy Forced Busy PHTMS 15 14 13 12 11 10 09 SynCal MDCL2 Trig0 08 07 06 Modifications: 04/17/04 G10 Numbering starts from 0

5. 4/17/04A. Sukhanov5 TML0 0)1)2)3)4)5)6)7)8) Heartbeat9) FBCosm10) 100 Hz11) SiCosm12) PNPP13) ZTrig14) CC15) Veto16) GND15) Veto L014) dbg.DP[0]13) dbg.L0Clk12) L0In11) L010) L09) PCALCosm8) PCALColl7) TinV6) HiPrio5) FBCosm4) ZGateExcl3) ZGate2) L0 pulse1) L0 pulse0) L016) GND CC clocked triggers To L1 logic, TOF TDC start Paddle+ZCALTDC start ZCAL ADC Gate TOF+Paddle ADC Gate TOF Excl ADC Gate 05 06 04 03 02 01 08 07 G12 TinV HiPrio 0) N/A1) Bucket32) N/A3) YDown4) YUp5) BDown6) BUp7) BRevolut8)9)10)11)12)13)14)15)16) - L0_COut + + L0_CIn - + DP - G05 16 15 14 13 12 10 09 08 Visual Sc13 L0Trg H4.7 ?White cable PCALCosm PCALColl x x x 17 V124B.7 Every third blue bucket, used to count Bucket Counter in L0 V124Y.4 V124Y.3 V124B.4 V124B.3 V124B.6 Blue Bucket #1. Used to clear Bucket counter in L0 Blue Polarization Up Blue Polarization Down Yellow Polarization Up Yellow Polarization Down 17)18)19) Modifications: 01/08/04 Correct L0->G5 04/14/04 Polarization bits on DP

6. 1/8/2004A. Sukhanov6 TML1 0) Lvl01) Pr12) Pr23) Pr34) Pr45) Pr56) Pr67) Pr78)9)10)11)12)13)14)15) Veto16) GND15) BusyL114) PrO.713) PrO.612) PrO.511) PrO.410) PrO.39) PrO.28) PrO.17) PrO.06) L1OR5) PrTest4) PrQ13) L1in2) FastClear1) L1Pulse0) Lvl116) GND 16 15 14 13 12 G12 PrQ1 L1in Fast Clear L1pulse L1 - L1_COut + + L1_CIn - G12.10 Modifications: 04/17/04 Show connection for BusyL1

7. 7/6/01A. Sukhanov7 Si L0/L1 G8.12 41us73us MDC1 SynCal G8.13 TTL/NIM G7CG4DG7D G12.9 MDC2 SynCal MDC1 INT L2 MDC2 INT L2 G8.14 G8.15 G12.11 NIM/ECL 41us73us G8.0 G8.1 G8.2 G8.3 MDC1 L2 MDC2 L2 MDC1 L1 MDC2 L1 G5.3 G5.4 Si L1 Si L2 CI.9 CI.8 CO.2 CO.3 EMM Calibration mode 560us 2560us Time=0

8. 7/6/01A. Sukhanov8 NIM Crates 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 08 09 10 11 12 13 14 15 08 09 10 11 12 13 14 15 08 09 10 11 12 13 14 15 726 PS G10 Translator L1 FB CO13BusyFB G12.12 VROC CO13BusyVROC G11.02 OutBusyL0 G12.10 OutBusyL1 G09.03 OutBusySi G06.03 OutBusyForce To EMM MDCL2For SiCaL Modifications: To L1 logic, TOF TDC start Paddle+ZCALTDC start ZCAL ADC Gate TOF+Paddle ADC Gate TOF Excl ADC Gate 05 06 04 03 02 01 08 07 L0 16 15 14 13 12 L1 PrQ1 L1in Fast Clear L1pulse L1 09 10 11 SynCal Busy L1 MDC* TinV HiPrio G12 Model 4616 TML1.CO15

9. 5/3/2004A. Sukhanov9 FASTBUS 1 2 3 Reset 1 2 3 NIM Out NIM In Busy Data Transfer L1 L2 L3 L4 G R G G LEDsLEMOs Busy Init Error EMMData Description Legend: L refers to LED, N – to NIM LEMO L4 ON: init_crate OFF: Run stopped N2 L2 : 1: 1)Read/Write mismatch, slot %d (r=%d,w=%d). DP=%x 2)ERROR: Load Next Event in slot %d\n",slot 0: Finished sending event L3: 1: start copying VME block9 0: finished VME block N3, L4 1: Start sending event 0: Finished sending event N1,L1 1: End of the Sparse Data Scan 0: Finished VME block 16 15 14 13 12 Token[05] Token[06] Token[07] HandShake TokClk 11 10 9 8 7 6 5 4 3 2 1 0 CI[15] CI[14] CI[13] CI[12] CI[11] CI[10] GND 16 15 14 13 12 CO[05] CO[06] CO[07] CO[09] CO[08] 11 10 9 8 7 6 5 4 3 2 1 0 Ack Dbg_HShck RQ Dbg_TokClk Dbg_Trans CO[10] GND CO[04] CO[03] CO[02] CO[01] CO[00] Token[00] Token[01] Token[02] Token[04] Token[03] From EMM CO[06:15] Busy VROC to EMMG10.13 Modifications: Shown Cin/COut + Cin - + COut -

10. 7/6/01A. Sukhanov10 Modifications 1/1/4. Cosmetic