1. Combinational Logic with Verilog Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer Organization and Architecture by L. Null & J. Lobur

2. 2 Combinational logic circuits give us many useful devices. One of the simplest is the half adder, which finds the sum of two bits. We can gain some insight as to the construction of a half adder by looking at its truth table, shown at the right. 3.5 Combinational Circuits

3. 3 As we see, the sum can be found using the XOR operation and the carry using the AND operation. 3.5 Combinational Circuits

4. 4 We can change our half adder into to a full adder by including gates for processing the carry bit. The truth table for a full adder is shown at the right. 3.5 Combinational Circuits

5. 5 Here’s our completed full adder. 3.5 Combinational Circuits

6. 6 Just as we combined half adders to make a full adder, full adders can connected in series. The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder. Today’s systems employ more efficient adders. 3.5 Combinational Circuits

7. 7 Decoders are another important type of combinational circuit. Among other things, they are useful in selecting a memory location according a binary value placed on the address lines of a memory bus. Address decoders with n inputs can select any of 2 n locations. This is a block diagram for a decoder. 3.5 Combinational Circuits

8. 8 This is what a 2-to-4 decoder looks like on the inside. If x = 0 and y = 1, which output line is enabled? 3.5 Combinational Circuits

9. 9 A multiplexer does just the opposite of a decoder. It selects a single output from several inputs. The particular input chosen for output is determined by the value of the multiplexer’s control lines. To be able to select among n inputs, log 2 n control lines are needed. This is a block diagram for a multiplexer. 3.5 Combinational Circuits

10. 10 This is what a 4-to-1 multiplexer looks like on the inside. If S 0 = 1 and S 1 = 0, which input is transferred to the output? 3.5 Combinational Circuits

11. 11 This shifter moves the bits of a nibble one position to the left or right. If S = 0, in which direction do the input bits shift? 3.5 Combinational Circuits

12. 12 Verilog Demo: Full Adder module fadd( output co, s, input ci, a, b ); wire a_xor_b; wire a_and_b; wire ci_and_a_xor_b; // common gate for both co and s xor u1( a_xor_b, a, b ); // remaining gates for co and u2( a_and_b, a, b ); and u3( ci_and_a_xor_b, ci, a_xor_b ); or u4( co, a_and_b, ci_and_a_xor_b ); // remaining gate for s xor u5( s, ci, a_xor_b ); endmodule

13. Demo Materials Verilog Files: – fadd.v fadd.v – fadd_tb.v fadd_tb.v – fadd_b.v fadd_b.v – fadd_4bit.v fadd_4bit.v – fadd_4bit_tb.v fadd_4bit_tb.v ModelSim Resources: – ModelSimGUIIntro.pdf ModelSimGUIIntro.pdf – TestbenchPrimer.pdf TestbenchPrimer.pdf – ModelSimTutorial.pdf ModelSimTutorial.pdf Verilog Resource: – VerilogWiki VerilogWiki – Verilog Quick Reference Verilog Quick Reference

14. Copyright © 2007 Elsevier 4- Introduction HDL Hardware description language (HDL): allows designer to specify logic function only. Then a computer-aided design (CAD) tool produces or synthesizes the optimized gates. Most commercial designs built using HDLs Two leading HDLs: – Verilog developed in 1984 by Gateway Design Automation became an IEEE standard (1364) in 1995 – VHDL Developed in 1981 by the Department of Defense Became an IEEE standard (1076) in 1987

15. Copyright © 2007 Elsevier 4- HDL to Gates Simulation –Input values are applied to the circuit –Outputs checked for correctness –Millions of dollars saved by debugging in simulation instead of hardware Synthesis –Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) IMPORTANT: When describing circuits using an HDL, it’s critical to think of the hardware the code should produce.

16. Copyright © 2007 Elsevier 4- Verilog Modules Two types of Modules: –Behavioral: describe what a module does –Structural: describe how a module is built from simpler modules

17. Copyright © 2007 Elsevier 4- Behavioral Verilog Example module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Verilog :

18. Copyright © 2007 Elsevier 4- Behavioral Verilog Simulation module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Verilog:

19. Copyright © 2007 Elsevier 4- Behavioral Verilog Synthesis module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Synthesis: Verilog:

20. Copyright © 2007 Elsevier 4- Verilog Syntax Case sensitive – Example: reset and Reset are not the same signal. No names that start with numbers – Example: 2mux is an invalid name. Whitespace ignored Comments: – // single line comment – /* multiline comment */

21. Copyright © 2007 Elsevier 4- Structural Modeling - Hierarchy module and3(input a, b, c, output y); assign y = a & b & c; endmodule module inv(input a, output y); assign y = ~a; endmodule module nand3(input a, b, c output y); wire n1; // internal signal and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inverter endmodule

22. Copyright © 2007 Elsevier 4- Bitwise Operators module gates(input [3:0] a, b, output [3:0] y1, y2, y3, y4, y5); /* Five different two-input logic gates acting on 4 bit busses */ assign y1 = a & b; // AND assign y2 = a | b; // OR assign y3 = a ^ b; // XOR assign y4 = ~(a & b); // NAND assign y5 = ~(a | b); // NOR endmodule // single line comment /*…*/ multiline comment

23. Copyright © 2007 Elsevier 4- Reduction Operators module and8(input [7:0] a, output y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; endmodule

24. Copyright © 2007 Elsevier 4- Conditional Assignment module mux2(input [3:0] d0, d1, input s, output [3:0] y); assign y = s ? d1 : d0; endmodule ? : is also called a ternary operator because it operates on 3 inputs: s, d1, and d0.

25. Copyright © 2007 Elsevier 4- Internal Variables module fulladder(input a, b, cin, output s, cout); wire p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin); endmodule

26. Copyright © 2007 Elsevier 4- Precedence ~ NOT *, /, %mult, div, mod +, -add,sub >shift >>arithmetic shift, >=comparison ==, !=equal, not equal &, ~&AND, NAND ^, ~^XOR, XNOR |, ~|OR, XOR ?: ternary operator Defines the order of operations Highest Lowest

27. Copyright © 2007 Elsevier 4- Numbers Number# BitsBaseDecimal Equivalent Stored 3’b1013binary5101 ‘b11unsizedbinary300…0011 8’b118binary300000011 8’b1010_10118binary17110101011 3’d63decimal6110 6’o426octal34100010 8’hAB8hexadecimal17110101011 42Unsizeddecimal4200…0101010 Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal)

28. Copyright © 2007 Elsevier 4- Bit Manipulations: Example 1 assign y = {a[2:1], {3{b[0]}}, a[0], 6’b100_010}; // if y is a 12-bit signal, the above statement produces: y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0 // underscores (_) are used for formatting only to make it easier to read. Verilog ignores them.

29. Copyright © 2007 Elsevier 4- Bit Manipulations: Example 2 module mux2_8(input [7:0] d0, d1, input s, output [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); endmodule Synthesis: Verilog:

30. Copyright © 2007 Elsevier 4- Z: Floating Output module tristate(input [3:0] a, input en, output [3:0] y); assign y = en ? a : 4'bz; endmodule Synthesis: Verilog:

31. Copyright © 2007 Elsevier 4- Delays module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule

32. Copyright © 2007 Elsevier 4- Delays module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule