1. Figure 4.1. The function f (x1, x2, x3) =  m(0, 2, 4, 5, 6).

2. Figure 4.2. Location of two-variable minterms.x x 1 2 x 1 x 2 1 m 1 m m m 1 2 1 m 2 1 m m 1 3 1 1 m 3
(a) Truth table
(b) Karnaugh map
Figure Location of two-variable minterms.

3. Figure 4.3. A simple logic function.1
Figure A simple logic function.

4. Figure 4.4. Location of three-variable minterms.

5. Figure 4.5. Examples of three-variable Karnaugh maps.1 2 x 3 00 01 11 10 1 1 f = x x + x x 1 3 2 3 1 1 1
(a) The function of Figure 2.18 x x 1 2 x 3 00 01 11 10 1 1 1 1 f = x + x x 1 3 1 2 1
(b) The function of Figure 4.1
Figure Examples of three-variable Karnaugh maps.

6. Figure 4.6. A four-variable Karnaugh map.

7. Figure 4.7. Examples of four-variable maps.

8. Figure 4.8. A five-variable Karnaugh map.

9. Figure 4.9. Three-variable function f =  m(0, 1, 2, 3, 7).

10. Figure 4.10. Four-variable function f =  m(2, 3, 5, 6, 7, 10, 11, 13, 14).

11. Figure 4.11. The function f =  m(0, 4, 8, 10, 11, 12, 13, 15).

12. Figure 4.12. The function f =  m(0, 2, 4, 5, 10, 11, 13, 15).x x 1 2 x x 3 4 00 01 11 10 00 1 1 x x x 1 3 4 01 1 1 x x x 2 3 4 11 1 1 x x x 1 3 4 10 1 1 x x x 2 3 4 x x x x x x 1 2 4 1 2 4 x x x x x x 1 2 3 1 2 3 .
Figure The function f =  m(0, 2, 4, 5, 10, 11, 13, 15).

13. Figure 4.13. POS minimization of f =  M(4, 5, 6).

14. Figure 4.14. POS minimization of f =  M(0, 1, 4, 8, 9, 12, 15).x x 1 2 x x 3 4 00 01 11 10 ( ) 00 x + x 3 4 01 1 1 ( x + x ) 2 3 11 1 1 1 10 1 1 1 1 ( x + x + x + x ) 1 2 3 4
Figure POS minimization of f =  M(0, 1, 4, 8, 9, 12, 15).

15. x 1 2 3 4 00 01 11 10 d
(a) SOP implementation x x 1 2 x x 3 4 00 01 11 10 ( x + x ) 2 3 00 1 d 01 1 d 11 d ( x + x ) 3 4 10 1 1 d 1
(b) POS implementation
Figure Two implementations of f =  m(2, 4, 5, 6, 10) + D(12, 13, 14, 15).

16. Figure 4.16. An example of multiple-output synthesis.2 x x 3 4 00 01 11 10 00 1 1 x 01 1 1 1 2 x 3 11 1 1 x 4 f 1 10 1 1 x 1 x 3
(a) Function f 1 x 1 x x 1 2 x x x 3 4 3 00 01 11 10 f x 2 00 1 1 2 x 3 01 1 1 x 4 11 1 1 1
(c) Combined circuit for f
and f 1 2 10 1 1
(b) Function f 2
Figure An example of multiple-output synthesis.

17. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure An example of multiple-output synthesis.

18. Figure 4.18. Implementation in a CPLD.

19. Figure 4.19. Implementation in an FPGA.

20. 7 inputs
Figure Using 4-input AND gates to realize a 7-input product term.

21. Figure 4.21. A factored circuit.x 1 x 2 x 4 x x 6 3 x 5 x 2 x 3 x 5
Figure A factored circuit.

22. Figure 4.22. A multilevel circuit.x 1 x 2 f 1 x f 3 2 x 4
Figure A multilevel circuit.

23. x 1 2 3 4 f g
Figure A multilevel circuit.

24. Figure 4.24. The structure of a decomposition.1 x 2 3 4 f g h
Figure The structure of a decomposition.

25. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure An example of decomposition.

26. Figure 4.26a. Implementation of XOR.1 x Å x 1 2 x 2
(a) Sum-of-products implementation x 1 x Å x 1 2 x 2
(b) NAND gate implementation
Figure 4.26a. Implementation of XOR.

27. Figure 4.26b. Implementation of XOR.
f = x1  x2 = x1x2 + x1x2 = x1(x1 + x2) + x2(x1 + x2) x 1 g x Å x 1 2 x 2
(c) Optimal NAND gate implementation
Figure 4.26b. Implementation of XOR.

28. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure Conversion to a NAND-gate circuit.

29. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure Conversion to a NOR-gate circuit.

30. Figure 4.29. Circuit for Example 4.10.

31. Figure 4.30. Circuit for Example 4.11.2 9 x 5 x P 3 4 f P 7 P 2 P P 3 P P 10 6 8 x 4 P 5
Figure Circuit for Example 4.11.

32. Figure 4.31. Circuit for Example 4.12.5 f x 5
(a) NAND-gate circuit
(b) Moving bubbles to convert to ANDs and ORs x 1 x 2 x 3 x 4 f x 5
(c) Circuit with AND and OR gates
Figure Circuit for Example 4.12.

33. Figure 4.32. Circuit for Example 4.13.

34. Figure 4.33. Representation of f (x1, x2) =  m(1, 2, 3).01 11 x1 x x f 1 2 x 1 1 2 1x 1 1 1 1 1 x 1 00 10
Figure Representation of f (x1, x2) =  m(1, 2, 3).

35. Figure 4.34. Representation of f (x1, x2, x3) =  m(0, 2, 4, 5, 6).

36. Figure 4.35. Representation of f =  m(0, 2, 3, 6, 7, 8, 10, 15).

37. Figure 4.36. Generation of prime implicants for

38. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure Selection of a cover.

39. Figure 4.38. Generation of prime implicants for

40. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure Selection of a cover.

41. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure Selection of a cover for the function in Example 4.15.

42. Figure 4.41. The coordinate *-operation.B A i 1 x i o A * B i i 1 o 1 1 x 1 x
Figure The coordinate *-operation.

43. Figure 4.42. The coordinate #-operation.B A i 1 x i e o e A # B i i 1 o e e x 1 e
Figure The coordinate #-operation.

44. Figure 4.43. An example four-variable function.1 2 1 2 x x x x 3 4 00 01 11 10 3 4 00 01 11 10 00 1 1 d 00 1 01 d 1 01 11 11 1 1 1 10 1 d 1 10 d 1 1 x = x = 1 5 5
Figure An example four-variable function.

45. Figure 4.44. Verilog code for the function in Figure 4.5a.
module func1 (x1, x2, x3, f);
input x1, x2, x3;
output f;
assign f = (~x1 & ~x2 & x3) | (x1 & ~x2 & ~x3) |
(x1 & ~x2 & x3) | (x1 & x2 & ~x3) ;
endmodule
Figure Verilog code for the function in Figure 4.5a.

46. Figure 4.45. Logic synthesis options in MAX+plusII.

47. Figure 4.46. Results of physical design.

48. Figure 4.47. Timing simulation results.
(a) Timing in an FPGA
(b) Timing in a CPLD
Figure Timing simulation results.

49. Please see “portrait orientation” PowerPoint file for Chapter 4
Figure A complete CAD system.

50. module example4_21 (x1, x2, x3, f); input x1, x2, x3; output f;
assign f = (~x1 & ~x2 & ~x3) | (~x1 & x2 & ~x3) |
(x1 & ~x2 & ~x3) | (x1 & ~x2 & x3) |
(x1 & x2 & ~x3);
endmodule 
Figure Verilog code for the function in Figure 4.1.

51. Figure 4.50. Implementation of the Verilog code in Figure 4.49.
(from interconnection wires) x x x
unused 1 2 3
PAL-like block 1 D Q
Figure Implementation of the Verilog code in Figure 4.49.

52. (from interconnection wires)x x x
unused 1 2 3
PAL-like block 1 D Q
Figure Implementation using XOR synthesis (f = x3  x1x2x3).
Figure Implementation using XOR synthesis (f = x3  x1x2x3).

53. Figure 4.52. Verilog code in Figure 4.49 implemented in a LUT.

54. module example4_22 (x1, x2, x3, x4, f); input x1, x2, x3, x4;
output f;
assign f = (~x1 & ~x2 & x3 & ~x4) | (~x1 & ~x2 & x3 & x4) |
(x1 & ~x2 & ~x3 & x4) | (x1 & ~x2 & x3 & ~x4) |
(x1 & ~x2 & x3 & x4) | (x1 & x2 & ~x3 & x4) ;
endmodule
Figure Verilog code for f1 in Figure 4.7.

55. module example4_23 (x1, x2, x3, x4, x5, x6, x7, f);
input x1, x2, x3, x4, x5, x6, x7;
output f;
assign f = (x1 & x3 & ~x6) | (x1 & x4 & x5 & ~x6) |
(x2 & x3 & x7) | (x2 & x4 & x5 & x7) ;
endmodule
Figure Verilog code for the function of section 4.6.

56. Figure 4.55. Two implementations of a 7-variable function.x x x x 1 1 3 6 x x 3 1 x x x + x x x 6 2 1 6 2 7 x 6 x x 1 7 x x x x x 4 1 4 5 6 x x 5 3 f x x 6 4 f x 5 x x x x 2 2 3 7 x 3 x 7 x 2 x x x x x 4 2 4 5 7 x 5 x 7
(a) Sum-of-products realization
(b) Factored realization
Figure Two implementations of a 7-variable function.

57. Figure P4.1. Expansion of implicant x1x2x3.

58. Figure P4.2. Circuit for problem 4.33.

59. Figure P4.3. Circuit for problem 4.34.