1. A Framework for Dynamic Energy Efficiency and Temperature Management (DEETM) Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/flexram

2. Micro’33, Dec 20002 Motivation  Increasingly high power consumption –High temperature –Inefficient use of energy  Limitations of existing approaches –Static optimizations –Coarse grain dynamic management (DPM) –Inefficient temperature control (sleep) –Independent targets: temp, energy efficiency

3. Micro’33, Dec 20003 Goal  Temperature: enforce limit while minimizing slowdown  Energy efficiency: maximize energy saving while exploiting performance slack Unified framework for Dynamic Energy Efficiency and Temperature Management (DEETM)

4. Micro’33, Dec 20004 Contribution: DTEEM Framework  Existing limitations: –static application –coarse grain dynamic –inefficient techniques –independent targets:  temperature control  energy efficiency  DEETM approach: –multiple techniques –dynamic –fine grain –order techniques for maximum efficiency –unified target

5. Micro’33, Dec 20005 DEETM Framework  Monitors temperature & execution slack  Runs decision algorithm periodically: {Thermal, Slack} components  Activates low-power techniques –dynamically –incrementally –in prioritized order

6. Micro’33, Dec 20006 Techniques  Instruction filter cache  Data cache subbanking  Voltage scaling  Voltage scaling: DRAM only  Light sleep

7. Micro’33, Dec 20007 Instruction Filter Cache Filter Cache Instruction Memory Processor Filter Cache L1 Cache Processor High power mode: Time: 1 Energy: E Filter Cache Instruction Memory Processor High power mode: Time: 1 Energy: E Filter Cache Instruction Memory Processor Low power mode: Time: 1 + mr*1 Energy: e + mr*E

8. Micro’33, Dec 20008 Techniques  Instruction filter cache  Data cache subbanking  Voltage scaling  Voltage scaling: DRAM only  Light sleep

9. Micro’33, Dec 20009 Chip Environment  Processor-in-memory  64 lean processors –2-issue static  Optimized memory hierarchy  Integrated thermal sensors and instruction counter Processor D-Cache I-Cache DRAM Bank Instruction Memory Processor DRAM Bank Interconnect

10. Micro’33, Dec 200010 Individual Techniques-E*D IFilter SubBank VoltFreq 0.7 Normalized Energy-Delay Product 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 Normalized Average Power 1.00.90.80.70.60.5 MemVolt Sleep

11. Micro’33, Dec 200011 Combinations - E*D 1.0 0.30.40.50.60.70.80.91.0 0.9 0.8 0.7 0.6 0.5 Normalized Average Power Normalized Energy-Delay Product VoltFreq IFilter Gradual

12. Micro’33, Dec 200012 Summary  Techniques ordered by efficiency (same order apply to both targets)  System applies techniques in order, dynamically and incrementally

13. Micro’33, Dec 200013 Thermal Algorithm Macrocycle

14. Micro’33, Dec 200014 Temperature Control - Limit

15. Micro’33, Dec 200015 Temperature Control - Slowdown

16. Micro’33, Dec 200016 Slack Algorithm Macrocycle Effective IPC*: frequency-adjusted Microcycle Every Macrocycle (HW/OS) The First Few Microcycles (HW)

17. Micro’33, Dec 200017 Slack - Energy Consumption

18. Micro’33, Dec 200018 Slack Misprediction

19. Micro’33, Dec 200019 Related Issues  Algorithm interaction  Selecting macrocycle  Handling Thermal Crisis situation  Reducing technique activation overhead  Flexible technique ordering  Hardware vs. software implementation

20. Micro’33, Dec 200020 Conclusions  Effective & efficient temperature control –very few macrocycles still over limit –27% longer execution vs. 98% (by sleeping)  Efficient & accurate fine-grain exploitation of execution slack –5% slack  27% energy saved –small slack misprediction