1. Memory Address Decoding
Design a 1MB memory system consisting of multiple memory chips
Solution 1:
256KB
256KB
256KB
256KB M1 M2 M3 M4 CS CS CS CS
A0 – A7
A18
2-to-4
decoder
A19 CS
IO/M

2. Memory Address Decoding
F F F F F M4
A19 A C
B F F F F M3
A19 A
7 F F F F M2
A19 A
3 F F F F M1
A19 A

3. Memory Address Decoding
Design a 1MB memory system consisting of multiple memory chips
Solution 2:
256KB
256KB
256KB
256KB M1 M2 M3 M4 CS CS CS CS
A2 – A19 A1
2-to-4
decoder A0 CS
IO/M

4. Memory Address Decoding M4 M3 M2
Advantage
Pipelining M1
A1A0 M4 M3 M2 M1