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Final Presentation Part-A
Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL Students: Danny Hofshi, Shai Shachrur Supervisor: Mony Orbach Winter 2012
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Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL
FPGA C++ PCIe Bluespec Scemi Bluespec HDL MIPS Students: Danny Hofshi, Shai Shachrur Supervisor: Mony Orbach Winter 2012
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Reminder FPGA C++ Bluespec Scemi Bluespec HDL
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Project Goals (from characteristic presentation)
Part A: Creating the Laboratory working environment. Hardware environment – RTL , interface to outer world ( pci - express ), Xilinx utilities. Software environment – simulation of a MIPS processor on the above RTL using simplified commands, the same environment will be used for emulation and simulation.
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Project Characterization
Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions We are here Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B
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What has been done Hardware infrastructure
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Hardware Linux Environment PCIe cable Virtex 5 FPGA
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What has been done RTL Design
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MIPS Design BlueSpec S C E M I - PCIe Clk control
Communicating with a c++ environment using generic interface BlueSpec Xilinx BRAM Co-Processor Xilinx BRAM
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The MIPS state machine
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What has been done Software environment
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Control interface Ability to Put & get data from the instruction memory. Ability to Put & get data from the data memory. Ability to control the MIPS operation (Co-processor) - stop - load PC, start & wait for interrupt - load PC & start for a specific number of cycles Retrieve performances (Co-processor). Number of clock cycles. Number of Instructions.
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SCEMI
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will generate an interrupt
Compiler Perl Script compiler – translate assembler code to our specific SCEM interface. addi $t1 $zero 2 addi $t2 $zero 2 add $t3 $t1 $t2 sw $t3 $zero 0 stop Processor commands Stop command will generate an interrupt Load PC Set PC Start
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Communication module C++
User work Flow Write Assembler Code & Data memory Type executable command Receive performances and data Communication module C++ addi $t1 $zero 2 addi $t2 $zero 2 add $t3 $t1 $t2 sw $t3 $zero 0 stop Compiler MIPS Data received
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On the PC
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Project Characterization
Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions We are here Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B
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Test program The Bubble sort Assembler code: // size of array addi $s0 $zero 64 // address counter addi $s1 $zero 0 // swap indicator start : addi $s2 $zero 0 start_in_iteration : lw $t0 $s1 0 lw $t1 $s1 4 // $t0=1 if we need to swap, $t0=0 else slt $t3 $t1 $t0 beq $t3 $zero no_swap sw $t0 $s1 4 sw $t1 $s1 0 // set swap indicator addi $s2 $zero 1 no_swap : beq $s1 $s0 end_iteration addi $s1 $s1 4 beq $zero $zero start_in_iteration end_iteration : beq $s2 $zero stop_sort addi $s0 $s0 -4 beq $s0 $zero stop_sort beq $zero $zero start
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Run The program Run on the CPU.
Typing the command line to compile and run the above code fpga]$ perl parser.pl -source bubble_sort.S -end -meminit mem_init.txt Starting to parse code ********* Running command_file.txt ************ (Writing Data to the I-MEM) Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading data to I-mem: Loading to arg register (Loading the start value of the MIPS Program counter) Load PC from arg register (Applying the start value to the PC) Start CPU (Starting the run on the MIPS) ####### Program run on CPU finished ####### (Receiving an interrupt from the PC) SceMi Service thread finished!
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Results 591 Cycles 122 Instructions 4.844 Cycles per instruction
********* inquiring check_mem.txt ************ (Reading the performance counters sort DATA) requesting number of cycles (Sending a data request to the Co-processor) number of clock cycles is 591 number of instructions is 122 {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h c} {data 32'h c resp_type 4'h1 resp_addr 32'h } {data 32'h d resp_type 4'h1 resp_addr 32'h } {data 32'h d resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h c} {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h a resp_type 4'h1 resp_addr 32'h } {data 32'h d resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h c} {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h d resp_type 4'h1 resp_addr 32'h c} {data 32'h resp_type 4'h1 resp_addr 32'h } {data 32'h resp_type 4'h1 resp_addr 32'h } Finished parsing 591 Cycles 122 Instructions 4.844 Cycles per instruction
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Remarks We can also run in simulation mode for RTL debug.
A full verification on the whole MIPS command set was made.
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We implement Meow prediction ?
Discussion
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