1. FF - ALICE Forum 22/09/04 Meeting ALICE radiation tolerance for COTS: introduction Some reasons for this meeting: A part very inner detectors (Pixels and SDD), ALICE has wide grey area; important decisions for the system depending on: risk analysis (how much system failure can be tolerated) economics (often parameter for ultimate decision of rad hard vs. COTS) system architecture (system redundancy and quantization+location) Electronics need to be validated for installation. safe margins performance/cost evaluate weak areas and probability of shut down time Never done ALICE survey before Aims: Status of COTS electronics in ALICE tested planned “overlooked” Regroup documents of tests already done by collaboration improve ALICE database (knowledge) stimulate commonalities (learn from others) compare and conform conclusions (validate results) Forum for discussion

2. FF - ALICE Forum 22/09/04 Meeting ALICE radiation tolerance for COTS (August 30 th - Room 161 1 009) Agenda (morning): 10h00 - Introduction (F. Formenti - 10 min) 10h10 - Radiation in the ALICE environment (A. Morsch - 20 min) 10h30 - SSD (M. Rossewij - 20 min) 10h50 - TPC Front End Card (L. Musa - 20 min) 11h10 - TPC Readout Control Unit (D. Rohrich - 20 min) TRD DCS Card (D. Rohrich - 15 min) PHOS (D. Rohrich - 5 min) 11h50 - TOF (P. Antonioli - 20 min) 12h10 / 13h30 Lunch Agenda (afternoon): 13h30 - Mu Arm Trk (F.F. summary - 20 min) 13h50 - FMD (B. Nielsen - 20 min) 14h10 - DAQ (C. Soos - 20 min) 14h30 - DCS (P. Chochula - 20 min) 14h50 - Trigger (P. Jovanovic - 20 min) 15h10 / 15h30 Coffee break 15h30 - Power supplies Caen (L. Periale - 20 min) 15h50 - Power supplies Wiener (B. Allongue - 20 min) 16h10 - Summary & discussion (F. Faccio & all - 40 min) Thanks to all participants!

3. FF - ALICE Forum 22/09/04 Running scenarios  4.2 10 15 particles produced/10years (mainly pp & ArAr high L)  worst case for TID (cumulated effect)  2400 particles/event and 3 10 5 event/sec produced in ArAr(high)  flux = 7.2 10 8 worst case for SEE (statistical effect) (for comparison: 1.1 10 8 PbPb and 2 10 7 pp)  Running shares  pp=50%, pPb=3%, ArAr(low)=0.5%, ArAR(high)=33%, PbPb=13.5% Other effects  2 10 14 particles produced by Beam-Gas inside ALICE  8 10 14 particles produced by Beam-Halo from tunnel machine  Beam loss at injection: <1% background at ITS and <3% at rack locations ~10% contribution each; ~ x2 uncertainty NOTE: No TPC in ArAr (high) Hyp: 10 beam loss / year

4. FF - ALICE Forum 22/09/04 Solenoid Moun dipole A Z Y DetectorDose total/10yrs [Rad]Fluence n total [cm -2 ]n_Ekin>20MeVChg_h>20MeV SPD275k-68k8.5 10 11 -6.0 10 11 3.4 10 11 - 1.4 10 11 4.0 10 12 -1.2 10 12 SDD25k-12k4.9 10 11 -4.5 10 11 3.7 10 10 - 2.6 10 10 3.8 10 11 -1.3 10 11 SSD5k-3k4.3 10 11 -4.2 10 11 2.0 10 10 - 1.7 10 10 5.0 10 10 -4.0 10 10 TPC1.6k-2203.9 10 11 -2.5 10 11 1.1 10 10 - 2.9 10 9 8.0 10 9 -1.3 10 9 TRD1801.6 10 11 2.0 10 9 7.2 10 8 TOF1201.1 10 11 1.6 10 9 5.3 10 8 HMPID508.6 10 10 1.2 10 9 3.0 10 8 PHOS408.2 10 10 -- V0330k-230k6.4 10 11 -17 10 11 T0330k-200k5.6 10 11 -19 10 11 FMD135k-230k-330k14 10 11 -6.5 10 11 -5.6 10 11 PMD26k3.1 10 11 MU TRK500-360-100-50-405.6 10 11 -4.1 10 11 -1.3 10 11- 0.9 10 11 -1.0 10 11 MU TRG260-2602.0 10 11 -2.0 10 11 Rack position Dose Max/10yr [Rad] Fluence Max [cm -2 ] 1MeV n-equ A0.946.7 10 7 B1.37.0 10 7 C1.27.2 10 7 D1.15.3 10 7 E0.618.6 10 7 F0.668.1 10 7 G1.42.0 10 8 H0.721.1 10 9 I0.381.1 10 8 J2.64.3 10 8 K0.741.2 10 8 L0.318.3 10 7 M1.23.0 10 7 B C D F E G H I J KLM A B C D 1 1 NOTE: Radiation for mid rapidity detectors at high radii, muon arm detectors and cavern is dominated by neutrons

5. FF - ALICE Forum 22/09/04 SSD detector (system) SSD sub-detector CTP DAQ DCS Slow control FEROM system L1/L2 TTC L0 (lvds) Busy (lvds) DDL fiber JTAG CAN ECM 1 10...13 x Analog JTAG (5xlvds) control (5xlvds) error (1xlvds) ECM 2 ECM 144 SSD-module 1 SSD-module 10…13 … ON-Detector electronics: Sensor modules  HAL25 chip  0.25  m rad tol. tech. End Cap Modules  Alcapone & Alabuf chips  0.25  m rad tol. tech. Power transistors for Voltage regulation  tested ( which type and results? High TID and high flux) Rack electronics (passerelle A): - FEROM system: ADModules  ADCs + 2xFPGAs + SRAM  which types? tested for rad tol? Link Modules  FPGA  which type? tested for rad tol? - Power supply: Planned CAEN SY1527  Not the CAEN planned configuration for rad tol. 0.25  m tech: should be OK Make tests with CAEN/ESS

6. FF - ALICE Forum 22/09/04 Assumed 1MeV n-equ.  fluence: 1 x 10 8 /cm 2 (rack position I) Hadron >20MeV fluence factor 10 lower: 1 x 10 7 /cm 2 Assumed running time: 10 7 sec. So flux hadron >20MeV: 1/cm2.sec. Assumed SEU cross section for FPGA and SRAM memories 10 -13 cm2/bit. (For the SRAM’s, this seems a fairly good estimate, for the FPGA’s no real data at this moment available). Also for the configuration PROM no real data available. Error rate using assumed cross section: 10 -13 /bit.sec: 10 % of FPGA’s total config memory: 34 Mega-bits o Error rate: 34E6x10 -13 = 3.4 10E-6 bits/sec. Aprox. 1 bit/ 80hrs o SEU can hang-up system. o Ferom has JTAG which allows partial readback and reconfiguration Offset and zero suppress memory: 40 Mega-bits o Error rate: 40E6x10 -13 = 4E-6 bits/sec. Aprox. 1 bit/70 hrs. o No system hang-up, SEU detected by readback after every run Event data memory: 14 Mega-bits (5% occupancy, All 4MEB in use) o Error rate: 14E6x10 -13 = 14E-7 bits/sec. Aprox. 1 bit/200 hrs. o No system hang-up, SEU detected with a parity mechanism FEROM crates are standard LHC VME crates with controller and memories as well! No data available? SSD detector (tolerance calculation) h>20MeV: rule of thumb, because not other data. Could be a reasonable first approx. Running time = 1 10 8 (42months) Do not use average flux value! Instead use running time for ArAr (high): 33% of total fluence/runtime, i.e. 33% 1 10 7 /2 10 6 =1.65/cm 2 sec Arbitrary cross sections. Maybe close value, but use real numbers or compared to similar cases. Check component databases. Typical configuration for the application is correct. Also good to check when full size used (worst and safest case; FPGA may be modified). Very good partial readback/reconfiguration: to implement For event data memory not necessary special needs (data flow) Validate controller COMMENTS

7. FF - ALICE Forum 22/09/04 TPC detector (system) Local Monitor and Control BOARD Controller RCU DCS ( 1 MB/s ) DDL ( 200 MB/s ) COUNTING ROOM COTS, FPGA ON DETECTOR Bus controller ( conf. & R/O ) FEC 128 ch 1 1 2 2 12 13 DCS int. (Ethernet) DAQ int. (DDL-SIU) Trigger int. (TTC-RX) FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch CUSTOM, COTS, FPGA DETECTOR Data Proc. and Memory PASSIVE COMPONENTS capacitors and resistors ~4400 FECs ~220 RCUs Sum Flux with E kin > 10MeV (cm -2 s -1 ) - simulation Layers1234 absorber side384268187129 Non-absorber side245149112 81 TID @ TPC in 1.6 krad @ TPC out 0.22 krad New more detailed simulations

8. FF - ALICE Forum 22/09/04 Test (I) 2002 65 MeV protons beam Proton Flux: 1·10 8, 5·10 8 p/cm 2 s UCL, Louvain-la-Neuve, Belgium Test (II) 2003 - 2004 Oslo Cyclotron Test (III) 2004 TSL (Uppsala) 38 and 180 MeV proton beam Proton flux ~ 10 7 – 10 8 protons/cm² s 25 and 28 MeV proton beam Proton flux ~ 10 7 – 10 8 protons/cm² s TPC detector (FEC tests) analog current standby digital current register errors PM errors DM errors SEU errors and other protocol errors ADC spikes and SEU error counter s test phase power status ALTRO Test Program KEY LEARNING POINTS  Large test campaign (all components on FEC & RCU, also many COTS for comparisons)  Preparation of several test cards (1 full year of PCB making)  Preparation of acquisition s/w  TID  x30 Alice dose (safe enough)  SEU acceptable for application, never latchup (FPGA reconfiguration, register reloading, Hamming protection) Special thanks to our collaborators

9. FF - ALICE Forum 22/09/04 TPC detector (RCU tests) For RCU: several FPGAs were tested (Altera and Xilinx) and compared with literature data. Errors per run (4 hours) per TPC system RCU3.7 SIU1.0 DCS1.9 Error rate is so low that one can cope with it, if SEUs can be detected instantenously or FPGA can be reconfigured in real-time (Xilinx Virtex II Pro)  Plan to migrate to Xilinx Cross section [cm 2 ] RCU FPGA – APEX20K400 6.0 x 10 -9  1.1 x 10 -9 SIU FPGA – APEX20K60 1.6 x 10 -9 DCS FPGA – EPXA1 2 x 10 -9 SEFI test with Xilinx Virtex-II Pro Reconfiguration started after 200 seconds: errors are corrected continuously (NOTE: test for protocol verification! Upsets >>Alice and slow reconfiguration) Fallback solution: FLASH based FPGA (Actel): ProASIC Plus FLASH Family FPGAs Preliminary irradidation results for Actel FPGA (device: APA075): Failure (probably latch-up) after fluence of 3.7 10 11 protons/cm 2  dose of 100k Rad Expected dose in 10 years of ALICE: ~ 570 Rad DAQ presentation Periodic reprogramming; data taking not affected

10. FF - ALICE Forum 22/09/04 TRD detector (DCS board) TRD DCS  180 Rad/10yrs & 5 10 8 p/cm 2 >25 MeV Complete list of devices tested Device TypeDevice Name FPGAEPXA1F484-C3 ARM CoreEPXA1F484-C3 Flash EPROMMX29LV320BTC-70 SDRAMMT48LC16C16A2 CPLDsLC4032ZC-75T48 Ethernet PhyLXT971ALC ADCAD7708BRU OptocouplersLTV357T Voltage Ref.AD1582ART Charge PumpREG711EA-5 LVDS DriverSN75LVDT390PW LVDS Receiv.SN75LVDS391PW Device TypeDevice Name RS422 DriverAM26LV31C RS422 Receiv.AM26LV32C WatchdogTPS3306-18DGK Voltage 3V3MIC29301-3.3BU or LP3962ES-3.3 Voltage 1V8MIC39151-1.8BU or LP3962ES-1.8 OptolinkTRR-1B43 OptolinkHFBR-2316T PLL Clock RecoveryTTCrx 3.2 Results where quite encouraging. We found no „No go“. Mean time to failure is : 21 days for one DCS board All components have been verified ~1/10 than TPC

11. FF - ALICE Forum 22/09/04 PHOS detector (system components)  FEE –APD + preamp (will go into beam August 31) –FEC (shaper + ALTRO) –TRU –TPC RCU  List of components that will be tested: 24LC256 MICROCHIP EEPROM GTL16612_TSSOP Philips GTL AD7417_TSSOP ANALOG DEVICES Temperature Sensor AD8039_SOIC ANALOG DEVICES OPAMP AD8544_SOIC ANALOG DEVICES OPAMP ALTRO-ST ST-Microelectronics ADC CY7C68013_ TQFP128 CYPRESS USB EP1K100-208_PQFP ALTERA FPGA EPC16 ALTERA FLASH KPC452 COSMO PHOTO COUPLER LM4041_1V2 NATIONAL REGULATOR LT1175_SOIC LINEAR REGULATOR MAX4454_TSSOP MAXIM-IC OPAMP MAX5308_TSSOP MAXIM-IC OPAMP MAX6033-A,5.0V MAXIM-IC REGULATOR MIC39151_TO263 MICREL REGULATOR MIC5239_SOIC-5.0 MICREL REGULATOR MIC5239_SOIC-ADJ MICREL REGULATOR MPC940L TQFP32_080 MOTOROLA REGULATOR OPA4364_TSSOP BURR-BROWN OPAMP 40MHZ, CFPT_125 C_MAC OSCILATOR TLC7733_SOIC Texas REGULATOR Dose = 40 Rad Shielding of 18 cm lead tungstate is not taken into account Full wish list of components. Many already tested by TPC+TRD Real case is safer

12. FF - ALICE Forum 22/09/04 HPTDC Output Fifo Readout Controller VME Interface Event Manager SRAM 32 TRG 32 x 15 L2r L2a L1 INPUTS (LVDS) ~700 TRMs Tested all TRM components during 2004 irradiations (up to 14krad) SRAM HPTDC LUT EVENT BUFFERS FLASH CC FIRMWARE FOR HPTDC LUT Functionalities implemented by an FPGA BOOT SEL WATCHDOG VME BUS ~20000 TDCs TOF detector (system on crates on-detector) NINO is 0.25  m tech: should be ok (120rad/10yrs) Other VME boards – DRM, LTM – use same components

13. FF - ALICE Forum 22/09/04 DeviceTOF (h -1 ) STRATIX CONF 15.7 SRAM (HPTDC LUT 1.97 Mbit) 4.2 SRAM (event buffers 4.0 Mbit) 4.3E-4 MTBF for Stratix too small despite of implementation of CRC check & reloading  moving to Actel ProAsic Plus APA600 HPTDC LUT (for linearization) will be periodically monitored (CRC) + reload from Flash Error rates in event buffers depend on L1 rate, L2 latency + TOF occupancy. Error rates here are for L1=1 KHz, 30% TOF occupancy (exp. 15%)). CRC check will be implemented. NOTE: Atmel µC acts as controller of FPGA power fault (latchups) and CRC_ERROR pin Monitor of errors in SRAM, FPGA internal memory + shift register logic check HPTDC Components TOF (h -1 ) CONF2.3 10 -2 READOUT FIFO (8Kb) 5.2 10 -5 L1 BUFFER (8Kbx4) 1.6 10 -4 MTBF (day) 1.8 800 260 TOF detector (TRM tests) MTBF (min) 3.8 14.3 2300 Planned additional irradiation campaign for Slow Control device. Choices: PMC Power PC Arm processor Excalibur FPGA Optical links

14. FF - ALICE Forum 22/09/04 MANU = ZONE A 500 Rad 5.6 10 10 cm -2 (n>2MeV) CROCUS = ZONE B ~170 Rad ~1.9 10 10 cm -2 (n>2MeV) TCI = ZONE C (LOW RADIATION) Components for irradiation Mu Trk detector (system) ? X X X X ?

15. FF - ALICE Forum 22/09/04 F.F. conclusions: Test campaign well started No problems in Mu Arm Trk Chambers for TID. Only SEE to test. Main custom chips (MANAS, MARC) are ok Important verification to be done in zone A is the ADC Work to be concluded: CROCUS crate electronics to test, because devices that can affect large part of system. Warning: if PMD uses same electronics then TID becomes 26kRad (not 500)! Mu Trk detector (first conclusions)

16. FF - ALICE Forum 22/09/04 FMD Module ON DETECTOR IN COUNTING ROOM VA 1 ring: 10/20 modules 2 Digitizers 1 RCU per ring system Full FMD: 70 modules 10 Digitizers 3 RCU’s VA read-out control VA read-out control TTC-RX BOARD CTRL FMD Digitizer ALTRO (16 ch) ALTRO (16 ch) ALTRO (16 ch) ALTRO (16 ch) ALTRO (16 ch) ALTRO (16 ch) Read-out CTRL Local Monitor and Control BOARD controller Bus controller ( conf. & R/O ) DCS int. (Ethernet) DAQ int. (DDL-SIU) Trigger int. (TTC-rx) Data Proc. and Memory DCS DDL TTC optical Link (Clock, L1 and L2 ) RCU Front-end bus ~ 3 m Front-end bus ~ 3 m  16 Control Network (I 2 C-serial link) Control Network (I 2 C-serial link) Trigger L0 NEAR PATCH PANEL Analog serial link (10 MHz)  0.5 m Analog serial link (10 MHz)  0.5 m FMD detector (system) Dose [Rad] h-  tot [cm -2 ] FMD38k-135k9-14 10 11 FMD24k-230k1.4-6.5 10 11 FMD190k-330k2.5-5.6 10 11 ≤0.5m ~3m Fluence ~ x2/x3 than TPC TID >> TPC # of units << TPC (TID ~ x300) (SEU ~ x 10)

17. FF - ALICE Forum 22/09/04 Electronics components of FMD:  Preamp-shaper-multiplexer on hybrid: VA1_ALICE in 0.35 µm technology by IDEAS, Oslo Rad.level 20k-330k Rad  FMD Digitizer: use ALTROs and TPC FEC schematics + VA1 read-out protocol with common 10 MHz clock, to be built at NBI, Copenhagen Need to be aware of higher rad. levels than at TPC Rad.level 10k-100k Rad  RCU identical to the one from TPC and PHOS Rad.level 1k-10k Rad FMD detector (results) v.0.35  m already tested up to few MRad Validation to be done! It should be OK

18. FF - ALICE Forum 22/09/04 Crystal oscillators (Pletronics, Saronix, CFP, Ecliptek) –TID 100 krad: negligible waveform change, no degradation Voltage regulators –Micrel: increased noise (< 6 mV), noise peaks (20 mV pp ), permanent damage (voltage shift) at 100 krad –Linear Technology: increased noise (< 6 mV), no damage Electrical transceivers: –Vitesse (GaAs): no damage up to 140 krad, 0 error @ 10 12 n/cm 2 –Texas Instruments (CMOS): no damage up to 400 krad Optical transceivers: –Agilent: no damage up to 22.8 krad, 13 error @ 10 12 n/cm 2 –Infineon: no damage up to 28.5 krad, 6 error @ 10 12 n/cm 2 DAQ (DDL-SIU component tests) Complete test of SIU

19. FF - ALICE Forum 22/09/04 Altera APEX 20K60E SERDES Conf. EPROM Optical Transceiver Data path (2x16 bits) + control BER + CL BER Covered by CRC Data path (serial) BERbit error rate CLconfiguration loss Present DDL implemented with ALTERA APEX-E (currently EP20K60E 160k gates - 0.18  ) Radiation tests have shown that we should expect 1 loss of configuration in 1 of the 400 DDL SIUs every hour With the present design, some of these loss will not be detected Actel APA 150 or 300 SERDES Optical Transceiver Data path (serial) Data path (2x16 bits) + control BER Covered by CRC PowerJTAG optional Possible re-design flash FPGA (ACTEL) DAQ (DDL component tests) Other “less prioritized” possibilities: Altera with CRC pin (status of configuration)  Cyclone Xilinx with real time re-programmability option  Virtex Make an ASIC Good compromise Safe by nature A proto possibly by end of year

20. FF - ALICE Forum 22/09/04 DCS (basic thoughts) FERO operation  a number of questions still need to be answered: –What detector specific commands need to be implemented? –How do we monitor and treat SEU ? –What are the sub-system and system dependencies? (switching order….) –What parameters need to be monitored and at what frequencies? –What are the expected actions if some parameters are out of range? (sometimes is sufficient to record the anomaly in the archive, sometimes we can recover the settings, in some cases the run must be stopped…) In some cases the DCS is expected to monitor for example local trigger counters – what happens if these are out of range ? –WHO and WHEN will starts the software developments on detector side, HOW and WHERE do we test the prototypes? Example (Class A device): typical problem requiring synchronization between online systems VR Failure (e.g. due to SEU) Recovery Action by DCS As a consequence FERO gets mis-configured DCS informs the DAQ and TRG via ECS DAQ reloads the FERO DCSDAQTRG FEROVR ECS Configuration DB 1 2 3 4 5 4 1 2 3 4 5 3 4 Failure by radiation is yet another error category to treat within a general DCS policy

21. FF - ALICE Forum 22/09/04 Trigger (basic thoughts) List of typical (critical?) components TTC boards – TTCvi, TTCex, TTCmi CPU (current choice: Concurrent Technologies, model CCTVP110 ) “Commercial” components (no control of radiation properties…) VME Controller FPGAs ALTERA EPM3512AFC256 EEPROM based,512 logic elements Board Logic ALTERA Cyclone EP1C12F324C SRAM based, 12k logic elements, configured from an on-board flash memory Flash memory Memories Am29LV081B, 8M bytes on-board FPGA configuration SnapShot Cypress CY7C1382B, 1Mx18 SSRAM, used only for monitoring DC-DC converter Bus transceivers Texas Instruments PT6441A 5V IN, 3.3V/6A Texas Instruments LVT162245 Note: TTC system never tested Component validation needs to be started soon. LTU available. Take advantage of existing data. Dose no problem, fluence not high.

22. FF - ALICE Forum 22/09/04 Power Supply (CAEN EASY) NOTE: Tests made to fulfill CMS environment (x100 more than ALICE) Not guaranteed rad tolerant Guaranteed rad tolerant Results Condi tions

23. FF - ALICE Forum 22/09/04 Power Supply (Wiener Maraton) Power module AC/DC Hostile zone Radiation + B field Protected zone Power supply box Aux PS Power module PFC PP Results from previous tests (2002 in PSI): –Power modules and AC/DC rectifier OK up to 14KRad and 1.10 11 p/cm 2. –Test without PFC (325VDC across switching transistors). –  P board failed. 2 power modules tested (March 2004): –1 equipped with STW9NB90 (9A, 900V) –1 equipped with STW12NK90Z (12A, 900V) For EMC issue, implementation of PFC: –Higher DC voltage across switching transistors (385V instead of 325V). –Transistors sensitive to SEE with Vds. –Replace switching transistors. Test conclusions: Both power modules worked within specifications up to the fluence 3 10 11 p/cm 2 and 42k Rad. No destructive single event occurred. The CANbus connection worked also fine during the irradiation (the controller board was not in the beam). The output voltage drifted a little (0.2%) due to temperature effect. Not guaranteed rad tolerant Guaranteed rad tolerant

24. FF - ALICE Forum 22/09/04 Conclusions An useful 1 st meeting on ALICE COTS radiation hardness. Good attendance of largest and critical detectors/systems. Radiation tolerance issues not treated with equal priority by different applications: Well understood:TPC, TRD (DCS), TOF, DAQ, Pixels and SDD (fully rad hard) On good way:FMD, Mu Trk, Power Supplies Good understanding, but further work:SSD, PHOS, DCS, Trig Need contact:all other detectors which regrettably could not participate Simulations: it would be appropriate to complete ALICE simulations with a final global picture including fluxes of particles (n and chg_h) for E>10-20MeV (also for crate area). Acknowledged large work done in ALICE with COTS. Planned collection of data in electronics coordination page for consultation.