1. Arithmetic in Computers

2. 2301274Chapter 4 Arithmetic in Computers2 Outline Data representation integers Unsigned integers Signed integers Floating-points Addition and subtraction Multiplication Division Floating-point operations

3. 2301274Chapter 4 Arithmetic in Computers3 Unsigned integers Binary representation in a word (4-bytes) Byte Ordering 200000000 is represented as follows 0000 1011 1110 1011 1100 0010 0000 0000 How to store it in memory addressed N Big Endian (big end is stored first) Little Endian (little end is stored first) 0000 1011 1110 1011 1100 0010 0000 0000 Address:N N+1 N+2 N+3 0000 0000 1100 0010 1110 1011 0000 1011 Address:N N+1 N+2 N+3

4. 2301274Chapter 4 Arithmetic in Computers4 Signed Integers Sign and magnitude representation Problems 2 representations of zero +0: 00000…000 -0: 10000…000 More complex adder 2’s complement representation Example: 4-bit representation 000001000-8 000111001-7 001021010-6 001131011-5 010041100-4 010151101-3 011061110-2 011171111-1 Problems The sizes of largest positive and smallest negative are different by 1. Sign bit magnitude Same as sign and magnitude representation

5. 2301274Chapter 4 Arithmetic in Computers5 Converting 2’s complement binary What is the 2’s complement representation of -3? Using 8-bit representation, 3 is 0000 0011. To get 2’s complement representation of -3 0000 0011 (3) bitwise complement 1111 1100 add 1 1111 1101

6. 2301274Chapter 4 Arithmetic in Computers6 Calculate value from 2’s complement For n-bit 2’s complement b n-1 b n-2 … b 1 b 0 Value: -b n-1  2 n-1 + ∑ 0 n-2 b i  2 i Ex: 1110 0111 represents the value -1000 0000 + 110 0111 =-128 + 103 = -25 If b n-1 =0, the value  0 (i.e. ∑ 0 n-2 b i  2 i ) If b n-1 =1, the value <0 (i.e. ∑ 0 n-2 b i  2 i – 2 n-1 ) For n-bit 2’s complement b n-1 b n-2 … b 1 b 0 Value: if b n-1 =0 ( b n-2 … b 1 b 0 ) 2 if b n-1 =1 Negative of the value of 2’s complement of ( b n-2 … b 1 b 0 ) 2 Ex: Consider 1110 0111. 2’s complement of 110 0111 is (001 1000 + 1) = 001 1001, which is 25. 1110 0111 represents -25.

7. 2301274Chapter 4 Arithmetic in Computers7 Advantages of 2’s complement representation Only one representation of zero. Most significant bit acts as sign bit. 2’s complement of 2’s complement of x is x. Simple for hardware design.

8. 2301274Chapter 4 Arithmetic in Computers8 Sign Extension In machine code, addi $t0, $t0, -3 is To copy -3 (FFFD) to be added to $t0, -3 needed to be extended to 32 bits (4 bytes). It is not possible to put 0’s in the upper 2 bytes Put 1’s in the upper 2 bytes 31 2625 2120 1615 0 oprsrtConst/addr 0 0 1 0 0 01 0 0 0 01 0 0 0 11 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 22 1 1 F F F D F DF F DF ? F DF F DF 0 F DF F DF

9. 2301274Chapter 4 Arithmetic in Computers9 Sign Extension Other operations which require sign extension. Load /store byte Load/store halfword

10. 2301274Chapter 4 Arithmetic in Computers10 Addition & Subtraction Binary addition/subtraction 0110 1100 108 0011 1101 + 61 + 1010 1001 169 0110 1100 108 0011 1101 - 61 - 0010 1111 47 0011 1101 61 0110 1100 - 108 - 1101 0001 -47 2’s complement addition/subtraction 0110 1100 108 0011 1101 + 61 + 1010 1001 169 0110 1100 108 1100 0011 + -61 + 0010 1111 47 0011 1101 61 1001 0100 +-108 + 1101 0001 -47

11. 2301274Chapter 4 Arithmetic in Computers11 n-bit adder n-bit subtractor n-bit adder … … x n-1 x n-2 x 1 x 0 z n-1 z n-2 z 1 z 0 C in C out … y n-1 y n-2 y 1 y 0 0 n-bit adder … x n-1 x n-2 x 1 x 0 C in C out … y n-1 y n-2 y 1 y 0 1 … z n-1 z n-2 z 1 z 0 xy x  y 000 011 101 110

12. 2301274Chapter 4 Arithmetic in Computers12 Adder/ subtractor y n-1 y n-2 y 1 y 0 n-bit adder … … x n-1 x n-2 x 1 x 0 sub z n-1 z n-2 z 1 z 0 C in C out xy x  y 000 011 101 110

13. 2301274Chapter 4 Arithmetic in Computers13 Overflow OperationOperand AOperand B Overflow if result is … A+B ++- --+ A-B +-- -++ Overflow occurs when the result of an operation is too large to fit in a word.

14. 2301274Chapter 4 Arithmetic in Computers14 Multiplication 01011001 59 16 00101011 x 2B 16 x 01011001 3D3 01011001 B2 00000000 EF3 01011001 00000000 01011001 0111011110011

15. 2301274Chapter 4 Arithmetic in Computers15 Multiplication Algorithm START Multiplier 0 =0? Add Multiplicand to Result Result=0; loop=0 Shift left Multiplicand once; Shift right Multiplier once; Increment loop loop<32? STOP F T F T

16. 2301274Chapter 4 Arithmetic in Computers16 Hardware: Sequential Multiplication Multiplicand (64-bit shift-left register) Multiplier (32-bit shift-right register) Result (64-bit register) test 32 loops 64-bit ALU test Multiplier 0

17. 2301274Chapter 4 Arithmetic in Computers17 Hardware: Parallel Multiplication 32-bit adder... Mplier 0 ·Mcand Mplier 3 ·Mcand Mplier 1 ·Mcand Mplier 30 ·Mcand Mplier 31 ·Mcand Mplier 2 ·Mcand prdt 0 prdt 2 prdt 3 prdt 1 prdt 30 prdt 63-31 1 bit 32 bit 01011001(Mcand) 00101011(Mplier)x 01011001 00000000 01011001 00000000 01011001 0111011110011

18. 2301274Chapter 4 Arithmetic in Computers18 Division 11101 1010 )100100101 1010 10000 1010 1101 1010 110 000 1101 1010 11

19. 2301274Chapter 4 Arithmetic in Computers19 Division Algorithm START Remainder<0? Shift left Quotient and set rightmost bit to 1 Remainder = Remainder – Divisor Shift right divisor once; Increment Loop loop<33? STOP FT F T Shift left Quotient and set rightmost bit to 0 Restore Remainder Initialization: Quotient = 0 Remainder = Dividen Divisor = Divisor<<32 Loop = 1

20. 2301274Chapter 4 Arithmetic in Computers20 Execution 0111 0000 1111 0000 1111 0000 1111 0000 remainder 1100 1100 1100 1100 0000 0000 0000 0000 divisor 0000 1010 1000 1010 1111 0000 1111 0000 0110 0110 0110 0110 0000 0000 0000 0000 0000 0000 quotient 0000 0000 0000 0001 Round12 0011 0011 0011 0011 0000 0000 0000 0000 3 0001 1001 1001 1001 1000 0000 0000 0000 0000 0000 0000 0010 4 0000 1100 1100 1100 1100 0000 0000 0000 0000 0000 0000 0100 5 0000 0110 0110 0110 0110 0000 0000 0000 0000 0000 0000 1000 6 0000 0100 0010 0100 1001 0000 1111 0000 0000 0011 0011 0011 0011 0000 0000 0000 0000 0000 0001 0001 7 0000 0000 1111 0001 0110 0000 1111 0000 0000 0001 1001 1001 1001 1000 0000 0000 0000 0000 0010 0011 8 0000 0000 1100 1100 1100 1100 0000 0000 0000 0000 0100 0110 Sol: 1000110100101101

21. 2301274Chapter 4 Arithmetic in Computers21 Hardware: Division Divisor (64-bit shift-right register) Quotient (32-bit shift-left register) Remainder (64-bit register) test 33 loops 64-bit ALU test Remainder

22. 2301274Chapter 4 Arithmetic in Computers22 Improved Hardware: Division Divisor (32-bit shift-right register) Remainder (64-bit register) test 32-bit ALU

23. 2301274Chapter 4 Arithmetic in Computers23 Floating-point Representation exponentfraction sign (-1) s  F  2 E Normalization is needed. F=1.xxxxxxxxx 2 Normalized number E = exponent – bias If bias=127. 000…0 represents -127 00…01 represents -1 011…1 represents 0 100…0 represents 1 11…10 represents 127 Why can’t 2’s complement be used? What does 111…1 represents?

24. 2301274Chapter 4 Arithmetic in Computers24 IEEE 754 floating point standard 313029282726252423 222120191817161514131211109876543210 exponentfraction sign (-1) s  F  2 E Single precision (bias=127) Double precision (bias=1023) 313029282726252423222120191817161514131211109876543210 exponent fraction sign 310 fraction

25. 2301274Chapter 4 Arithmetic in Computers25 Floating-point value 313029282726252423 222120191817161514131211109876543210 exponentfraction sign Value=(-1) sign  (1.b 22 b 21 …b 0 ) 2  2 ((b 30 b 29 …b 23 ) 2 -bias) Single precision

26. 2301274Chapter 4 Arithmetic in Computers26 Normalization If a floating-point is in the form of 0.xxx  2 yyy, it is denormalized. To normalized F  2 E Repeat { F=F<<1 E=E-1 } until the MSB of F is 1 F=F<<1 E=E-1

27. 2301274Chapter 4 Arithmetic in Computers27 Special Cases for Floating-point Range Max. number, min. number Precision The last digit represented in the number Special values (IEEE standard)  exponent =(1…1) 2  reserved Fraction = 0 NaN (Not a Number) exponent =(1…1) 2  reserved Fraction  0 Overflow occurs when the positive exponent is too large. Underflow occurs when the negative exponent is too large.

28. 2301274Chapter 4 Arithmetic in Computers28 Floating-Point Addition Let X= F  2 B and Y= G  2 D, where F=1.A, G= 1.C To add X and Y If B<D find G’=G  2 D-B and Y= G  2 D =G’  2 B. Z = (F+G’)  2 B. If B>D find F’=F  2 B-D and X= F  2 B =F’  2 D. Z = (F’+G)  2 D. If B=D Z = (F+G)  2 B. Finally, normalized Z.

29. 2301274Chapter 4 Arithmetic in Computers29 Floating-Point Multiplication Let X= F  2 B and Y= G  2 D, where F=1.A, G= 1.C Let Z= X  Y = F  2 B  G  2 D = (F  G)  2 B+D. To multiply X and Y find F  G, and B+D. Z = (F+G)  2 B+D. Finally, normalized Z.

30. 2301274Chapter 4 Arithmetic in Computers30 Floating point operand in MIPS 32 floating-point registers $f0, $f1, …, $f31 Size of each register = 32 bits 1 single-precision data can be stored in 1 floating- point register. 1 double-precision data must be stored in a pair of floating-point registers. For double-precision data, $f0 refers to the pair $f0,$f1.

31. 2301274Chapter 4 Arithmetic in Computers31 Floating-point Arithmetic InstructionExampleMeaning FP add single add.s $f2,$f4,$f6 $f2 = $f4 + $f6 FP subtract single sub.s $f2,$f4,$f6 $f2 = $f4 - $f6 FP multiply single mul.s $f2,$f4,$f6 $f2 = $f4 * $f6 FP divide single div.s $f2,$f4,$f6 $f2 = $f4 / $f6 FP add double add.d $f2,$f4,$f6 $f2 = $f4 + $f6 FP subtract double sub.d $f2,$f4,$f6 $f2 = $f4 - $f6 FP multiply double mul.d $f2,$f4,$f6 $f2 = $f4 * $f6 FP divide double div.d $f2,$f4,$f6 $f2 = $f4 / $f6

32. 2301274Chapter 4 Arithmetic in Computers32 Floating-point Data Transfer InstructionExampleMeaning load word coprocessor 1 lwc1 $f1,100($2) $f1 = Memory[$2+100] store word coprocessor 1 swc1 $f1,100($2) Memory[$2+100] = $f1 load double l.d $f0,100($2) $f0 = Memory[$2+100] $f1 = Memory[$2+104] store double s.d $f0,100($2) Memory[$2+100] = $f0 Memory[$2+104] = $f1

33. 2301274Chapter 4 Arithmetic in Computers33 Floating-point Comparison InstructionExampleMeaning branch on FP true bc1t 100 if (cond == 1) go to PC+4+100 branch on FP false bc1f 100 if (cond == 0) go to PC+4+100 FP compare single (eq,ne,lt,le,gt,ge ) c.lt.s $f2,$f4 if ($f2 < $f4) cond=1; else cond=0 FP compare double (eq,ne,lt,le,gt,ge ) c.lt.d $f2,$f4 if ($f2 < $f4) cond=1; else cond=0

34. 2301274Chapter 4 Arithmetic in Computers34 Note Data and program are stored in memory. How to interpret what a bit sequence means depends on what it represents An assembly instruction See Instruction formats, fields, op codes Data Unsigned integers: binary numbers Signed integers : 2’s complement numbers Floating-points: Exponent Fraction Sign

35. 2301274Chapter 4 Arithmetic in Computers35