1. Power modeling flow for a power analysis at system level Cyril Chevalier, Audrey Le-Clercq, Diana Moisuc STMicroelectronics Philippe Garrault Docea Power

2.  Power modeling at system level: need, usage and requirement  IP power characterization  IP power modeling: HW power model, Use case power model  Hierarchical power modeling  Use case power modeling  Some system level results Content

3. ESL power analysis general purposes Power aware SW simulation Trace from SW simulation or board validation Trace from SW simulation or board validation SW Use cases modeling Power model Architectural performance model Thermal model TLM/SystC virtual platform Aceplorer POWER ARCHITECTURE EXPLORATION POWER BUDGET TRACKING THERMAL ANALYSIS POWER MANAGEMENT SW HELP TO DECISION

4. Panic chez l’architect Sure, our devices are very competitive with regards to power! Marketing to Customer:Marketing to System Architects: I need to model the power behaviour of the whole SoC/chipset. I need to model all the use cases!! How do I get the data? Can I trust the data I am getting? Can I trust my model?

5. System design flow Early architecture UC Power Tracking Architecture validation Power aware SW development PM SW debug Specification Validation TLM SystC platform availability RTL PG Dynamic thermal management simulation Power architecture model SystC-TLM platformPerformances architecture model Thermal model

6. System modeling for accuracy : a bottom-up flow System architecture Power estimation Performance analysis Soc architecture AMS architectureRF architecture Power model for estimation Sub-system 1 Sub-system 3 3rd party IP IP estimation Sub-system 2 IP estimation Use case description Sw constraints Power model Use case analysis IP power estimatio n IP power estimatio n IP power estimatio n IP power estimation

7. IP Power characterization for power modeling  Power(Power State i ) = f(Param 1, Param 2,....) Parameters: voltage, clock frequency, activity, process and temperatureParameters: voltage, clock frequency, activity, process and temperature  IP Characterization process: Power states & parameters identification Simulations, Characterization: Simulations, Measures Conditions & Power figures reporting in a Power Card Power model library Architect Designer

8. Example: Audio Sub-System 5 power states  5 power states: Idle,Idle, Always On,Always On, Music Playback,Music Playback, CS Call,CS Call, Max ActivityMax Activity Parameters  2 Power supplies: Vlogic,Vlogic, VmemVmem  3 clocks P(CS Call) = f(Vlogic, Vmem, Clock1, Clock2, Clock3)

9. IP level: Simulation environment IP power characterization flow Gate Pwr Estimate Activity file per power state : PS i RTL Pwr Estimate IP design flow Flow inputs levels Param_1 … Param_nDynamic Power PS 1 PS 2 … PS n Dynamic pwr Per pwr state Power figures collection : IP Power card Power states VLeak PS 1 PS 2 … PS n Leakage per power state Validation environment Pwr Measures Specification targets, IP description

10. Power model generation IP Power Model generation VCkFunc param Dyn Power PS 1 PS 2 … PS n VLeak PS 1 PS 2 … PS n Each IP must have its Power Card IP power model library IP Power Model IP Power Model i Power model update Parameters default values Parameterized current equations Parameters IP Power card IP Power Model Equations of Dynamic and Leakage Power consumption Aceplorer

11. IP power use case model Pwr(PS1) Pwr(PS2) Pwr(PS3) Pwr(PS4) Pwr(PS5) Pwr(PS6) Pwr(PS7) IP power model IP power states Pwr(PS1) Pwr( PS4) t1 t2 t3 t4 Pwr( PS2) Pwr( PS1) Pwr (W) PS1 PS4PS2PS1 t1 t2 t3 t4 Scenario IP power model library IP Power Model i IP UC Power Model i

12. Hierarchical model & scenario creation instantiation Hierarchy capture Top MC1 MC2 MC3 C1 C2 C3 Vdd1Vdd2 Aceplorer IP power model library Power model UC model TL-PS1TL-PS4TL-PS2TL-PS1 time MC1-PS1MC1-PS2 C3-PS4C3-PS2C3-PS1 MC1 C2 Modeling Interface Scenario description Aceplorer

13. Conclusion Power modeling flow  Formal modeling flow : model standardization Data traceabilityData traceability Easier model debugEasier model debug High readability : communication tool bw many usersHigh readability : communication tool bw many users  Fast system power model development  Upgradeable models for accuracy as needed Next work  use cases power trace usage  Use cases development for power model correlation with on board validation