1. BTW 2010 An IEEE 1149.7 Update : Standard Reduced-pin and Enhanced-functionality Test Access Port and Boundary-Scan Architecture Adam W Ley ASSET InterTech, Inc. 2010 Sep 15

2. BTW 2010 2 Acknowledgements  the P1149.7 working group  Stephen Lau of Texas Instruments  Gary Swoboda of Texas Instruments who shall be recognized as the technical architect and principal author of 1149.7

3. BTW 2010 3 Outline  What is IEEE 1149.7?  IEEE 1149.7 Key Objectives  How it Works Selection Hierarchy Capability Classes

4. BTW 2010 4 Outline  What is IEEE 1149.7?  IEEE 1149.7 Key Objectives  How it Works Selection Hierarchy Capability Classes  Implications for Debug  Implications for Test

5. BTW 2010 What is IEEE 1149.7?

6. BTW 2010 6 What is IEEE 1149.7 ?  Formally, Standard for Reduced-pin and Enhanced- functionality Test Access Port and Boundary-Scan Architecture

7. BTW 2010 7 What is IEEE 1149.7 ?  NOT a replacement for IEEE 1149.1 rather, an adaptation and extension of it, built upon it’s foundation and legacy  Preserves the original Boundary-Scan Architecture -particularly for use in test and in-system configuration  Maintains compatibility with the standard Test Access Port while offering Reduced Pin Count -absolute minimum of 2 pins (down from 4) Enhanced Functionality -particularly for use in applications debug

8. BTW 2010 8 What is IEEE 1149.7 ?  Scope Link between 1149.1-based Debug and Test Systems and Target Systems Additional layer adapts for new functionality and features Link behavior includes timing, protocols, and functionality of the adapters Does not modify or create inconsistencies with IEEE 1149.1 (JTAG) A compliant superset the IEEE 1149.1  Status Formally adopted by IEEE-SA Standards Board 2009 Dec Published by IEEE on 2010 Feb 10  Sightings Adopted by MIPI and NEXUS 5001 Design and Validation support from IPextreme and Globetech Semiconductor support announced by TI, Freescale, ST

9. BTW 2010 9 1149.1 - The Test Architecture  Boundary scan and other test data registers operate under control of instruction register  Data is scanned from TDI to TDO through selected test data register or instruction register under control of Test Access Port (TAP) controller  TAP operates synchronously to TCK using TMS for state selection CORE ID Register Bypass Register Instruction Register Decode Logic DR TDI IR TDO TMS TCK TAP Controller

10. BTW 2010 10 1149.1 - The TAP Controller  16-state TAP provides 4 major operations: RESET RUN-TEST SCAN-DR SCAN-IR  Scans consist of 3 primary steps: CAPTURE SHIFT UPDATE

11. BTW 2010 11 Adaptation of 1149.1 to 1149.7 1149.1 IC 1149.7 chip 1149.1 “core” 1149.7 adapter “before”“after”

12. BTW 2010 IEEE 1149.7 Key Objectives

13. BTW 2010 13 IEEE 1149.7 Key Objectives  For Test Maintain compliance with 1149.1 to preserve the industry test infrastructure  For Applications Debug Extend/ Advance capability to provide: -Reduced Power Modes – Defined test logic power down -Improved Performance – Shortened multi-chip chains – Glueless “star” configuration -Reduced Pins -Links to “Instrumentation”

14. BTW 2010 14 SiP die 1 die 2 die 3 TCKCTMSC Through-silicon vias Star topology for a 3-die SIP

15. BTW 2010 How it Works

16. BTW 2010 16 TDI TDO TCK TMS Conventional series topology - highlighting the star wiring for TCK/TMS

17. BTW 2010 17 Notional view of the 1149.7 architecture APU PSL EPUSTL RSU TAP.7 TDI(C) TDO(C) nTRST TCK(C) TMS(C) TAP.7 Controller Advanced Protocol Unit Pin Sharing Logic Extended Protocol Unit System Test Logic Reset and Selection Unit

18. BTW 2010 How it Works - Selection Hierarchy

19. BTW 2010 19 Selection Hierarchy  Technology Where the 1149.7 technology can be placed offline, the TAP.7 signaling can be shared with other technologies  Topology Where the constituent 1149.7 devices can be placed offline (a function required for T3 and above), the TAP.7 signaling can be shared among any topology branches, whether series, star-2, or star-4  Adapter (i.e., ADTAPC) 1149.7 devices comprising a selected topology branch will share TAP.7 signaling and, where the topology branch is star-2 or star-4, a given device may be selected for a given operation  Chip (i.e., CLTAPC) For a selected ADTAPC, the CLTAPC may be offline and will require selection when it must be operated  Core (i.e., EMTAPC) For a selected CLTAPC, given EMTAPC(s) of interest may be offline and will require selection when it (they) must be operated

20. BTW 2010 How it Works - Capability Classes

21. BTW 2010 21 Key Features of the Capability Classes  Six classes of 1149.7 test access ports (TAP.7s), T0 - T5  Incremental capability, each higher builds upon the lower  Class T0 – foundation 1149.1 behavior from start-up, even where multiple on-chip TAPs  Class T1 – commands and registers common debug functions, features to minimize power consumption  Class T2 – scan formats improved scan performance, optional hot-connection capability  Class T3 – direct addressability operation in four-wire Series or Star Scan Topology  Class T4 – packetization of scan data (2-pin scan formats) two-pin or four-pin interface; two-pin operation serializes 1149.1 transactions and provides for higher test clock rates  Class T5 – transport of non-scan data (2-pin mode) data transfers concurrent with scan, utilization of functions other than scan, and control of TAP.7 pins for custom debug technologies

22. BTW 2010 22 IEEE 1149.7 hierarchy of classes

23. BTW 2010 How it Works - Capability Classes Class T0 – foundation

24. BTW 2010 24 Class T0  TAP behavior is IEEE 1149.1 compliant N-bit IR 1-bit DR for bypass instruction IDCODE requirement is mandatory (32 bit path) Mandatory instructions behave as specified in 1149.1 specification  Interface behavior is compliant between: Test-Logic-Reset TAP state and First operation that changes the IR and DR scan path configuration to operate appear as multiple TAPs connected in Series with separate instruction register and data register scan paths (similar to a board on chip).

25. BTW 2010 How it Works - Capability Classes Class T1 – commands and registers

26. BTW 2010 26 Test-Logic- Reset 1 0 Run-Test-Idle 0 1 Select-DR- Scan Capture-DR Exit1-DR Exit2-DR Update-DR Shift-DR 0 Pause-DR 0 1 1 0 1 0 0 0 1 1 1 10 Select-IR- Scan Capture-IR Exit1-IR Exit2-IR Update-IR Shift-IR 0 Pause-IR 0 1 1 0 1 0 0 0 1 1 1 10 a TAP FSM trajectory for ZBS, path a

27. BTW 2010 27 Test-Logic- Reset 1 0 Run-Test-Idle 0 1 Select-DR- Scan Capture-DR Exit1-DR Exit2-DR Update-DR Shift-DR 0 Pause-DR 0 1 1 0 1 0 0 0 1 1 1 10 Select-IR- Scan Capture-IR Exit1-IR Exit2-IR Update-IR Shift-IR 0 Pause-IR 0 1 1 0 1 0 0 0 1 1 1 10 b TAP FSM trajectory for ZBS, path b

28. BTW 2010 28 Test-Logic- Reset 1 0 Run-Test-Idle 0 1 Select-DR- Scan Capture-DR Exit1-DR Exit2-DR Update-DR Shift-DR 0 Pause-DR 0 1 1 0 1 0 0 0 1 1 1 10 Select-IR- Scan Capture-IR Exit1-IR Exit2-IR Update-IR Shift-IR 0 Pause-IR 0 1 1 0 1 0 0 0 1 1 1 10 a b T1, TAP FSM trajectories for Zero-Bit Scans

29. BTW 2010 29 T1, Zero-Bit Scans Create Control Levels Count the number of Zero- Bit-Scans (ZBS) to change the definition of BYPASS instruction. Lock control level when the Shift-DR state is reached. Key: 1…. 2…. Lock Control Level at 2. BYPASS IR Register

30. BTW 2010 30 T1, Commands & Registers  Accepted at Control Level 2  Controller commands are 10-bit values. They consist of 2 consecutive DR scans while the controller is locked at control level 2.  Command Part 1 (CP1) provides the command  Command part 2 (CP2) provides the immediate operand or lower 5 bits of the command  Can create a three-part command Can send/receive data values other than values embedded in CP2. Crated by appending an additional DR Scan after the CP1 and CP2 to transport a data value. 5-bit op-code 2 part Command 1 st DR Scan creates X bits 3 part Command 3 rd DR Scan Access an EPU scan path CP1 5-bit operand 2nd DR Scan creates CP2

31. BTW 2010 How it Works - Capability Classes Class T2 – scan formats

32. BTW 2010 32 T2, Scan Formats  Adds 3 Scan Formats: Change the operation of scan JSCAN0: Provides compliant IEEE 1149.1 operation JSCAN1: Provides “Hot” connection and disconnection protection JSCAN2: Improved performance for Series connected devices. Write only register is used to specify the scan format  These 3 formats use two features: Chip Level Bypass TAP Selection

33. BTW 2010 How it Works - Capability Classes Class T3 – direct addressibility

34. BTW 2010 34 TCK(C) TMS(C) TDIC TDOC T3, Star-4 Topology

35. BTW 2010 35 T3, Elements of the TAP.7 Controller Address (TCA) MSBLSB 342726111000 NODE_ID[7:0]DEVICE_ID[27:12] Part Number DEVICE_ID[11:0] Manufacturer

36. BTW 2010 How it Works - Capability Classes Class T4 – 2-pin scan formats

37. BTW 2010 37 TCKC TMSC Star-2 Topology

38. BTW 2010 38 TCKC nTDITMSTDOnTDITMSTDOnTDITMSTDO TMSC state T4, Scan packet serialization, OScan1

39. BTW 2010 39 TCKC nTDI TMSC Shift-xR state T4, Scan packet serialization, OScan7

40. BTW 2010 How it Works - Capability Classes Class T5 – transport of non-scan data (2-pin mode)

41. BTW 2010 41 T5, Transport  Transport packet type is added to support: Background Data Transfers (BDX) Custom Data Transfers (CDX)  When BDX is enabled: During link IDLE time, instrumentation data is transmitted Transport packets are attached to the IDLE, PAUSE, or UPDATE states DTC to target, target to DTC, Bi-Directional or custom transfers Non-scan data is transferred (ex: instrumentation data)  When CDX is enabled: Instead of SCAN, an alternate protocol is allowed to use the link during SHIFT-DR TAP states Transport packets are attached to the IDLE, PAUSE, or UPDATE states Custom transfers on a clock by clock basis Non-scan data is transferred

42. BTW 2010 Implications for Debug

43. BTW 2010 43 Debug Considerations  Ease  Efficiency

44. BTW 2010 44 Debug Features  Access consolidation  Hot-plug immunity  System interrogation  Optimization of scan throughput  Improved link utilization

45. BTW 2010 45 Each participating chip drives its AT[n] on wired-OR basis (logic 1 inactive) TDO  AT[n] Start n=0 All supporting chips without CID participate; chips with a CID do not participate. For each participating chip, its aliasing target AT[35:0] = TCA[34:0] + 0 n=36? Final n? Qualify AT[n] Each chip that detects that its AT[n] != TDO drops out n++ Next n The chip that matched all 36 bits of its AT to all 36 bits of TDO wins and gets the CID End Winner Gets CID Y N Enumeration of controller ID

46. BTW 2010 Implications for Test

47. BTW 2010 47 Test-Logic- Reset 1 0 Run-Test-Idle 0 1 Select-DR- Scan Capture-DR Exit1-DR Exit2-DR Update-DR Shift-DR 0 Pause-DR 0 1 1 0 1 0 0 0 1 1 1 10 Select-IR- Scan Capture-IR Exit1-IR Exit2-IR Update-IR Shift-IR 0 Pause-IR 0 1 1 0 1 0 0 0 1 1 1 10 TAP FSM trajectory for series topology scans

48. BTW 2010 48 Test-Logic- Reset 1 0 Run-Test-Idle 0 1 Select-DR- Scan Capture-DR Exit1-DR Exit2-DR Update-DR Shift-DR 0 Pause-DR 0 1 1 0 1 0 0 0 1 1 1 10 Select-IR- Scan Capture-IR Exit1-IR Exit2-IR Update-IR Shift-IR 0 Pause-IR 0 1 1 0 1 0 0 0 1 1 1 10 TAP FSM trajectory for star topology scans - for series equivalency

49. BTW 2010 49 module Chip A Chip B endpoint Example 1149.7 component comprising a test module with two test endpoints

50. BTW 2010 50 attribute COMPONENT_CONFORMANCE_ADAPTER attribute COMPONENT_CONFORMANCE_STL attribute TAP_CLASS attribute TAP_SCAN_CLOCK_COMPACT attribute TAP_SCAN_MODE_COMPACT attribute TAP_SCAN_IN_COMPACT attribute TAP_SCAN_OUT_COMPACT attribute TAP_SCAN_RESET_PD attribute CNFG0_REGISTER attribute CNFG1_REGISTER attribute CNFG2_REGISTER attribute CNFG3_REGISTER BSDL.7 new attributes (above BSDL.1)

51. BTW 2010 51 attribute COMPONENT_CONFORMANCE_MODULE attribute MEMBERS attribute MEMBERS_PORTMAP attribute MEMBERS_NODEIDS HSDL.7 attributes (above BSDL.7)

52. BTW 2010 52 Conclusion  IEEE 1149.7 is a complementary superset of IEEE 1149.1 (JTAG) Reduced pins and enhanced functionality  Built on the foundation of 1149.1 rapid adoption possible/ expected  Compatibility for test  Interfacing multiples cores on SOC die in SIP packages for POP  Debug improvements hot-plug immunity power management optimization of scan throughput access to debug instrumentation access to custom debug technologies

53. BTW 2010 53 Further Discussion  Where have you seen 1149.7 chips on your boards?  Where will you see 1149.7 chips on your boards?  Where would you like to see 1149.7 chips on your boards?

54. BTW 2010 54 Your Speaker Adam W Ley earned the BSEE degree at Oklahoma State University, Stillwater OK, in 1986. Upon graduation, he joined Texas Instruments Incorporated (TI), Sherman TX, as a product engineer, in the Logic Products division, for the test and characterization of new logic families. He first became involved in scan test in 1991 while he was technical lead for TI’s efforts to develop and bring to market its line of boundary-scan logic products. Since engaging with the original IEEE 1149.1 working group in 1993, he served that group as Vice Chair and, for its 2001 revision, as Technical Editor. He also has been an active participant in the work of nearly all related standards, to include IEEE 1149.4, IEEE 1149.5 (withdrawn), IEEE 1500, IEEE 1149.6, PICMG MicroTCA, and, currently, IEEE 1149.4 (revision), IEEE p1581, IEEE 1149.7, “SJTAG” (system JTAG), and iNEMI boundary-scan adoption. In 1999, he joined ASSET InterTech, Inc. (ASSET), Richardson TX, as a member of its Corporate Applications team. He was subsequently named Director – Corporate Applications in the same year. Since 2001, he has served as Chief Technologist – Boundary Scan for ASSET. In this role, he is responsible for ensuring that ASSET’s boundary-scan technology sets the pace that leads the industry.

55. BTW 2010 55 entity My_Dot7_IC is generic (PHYSICAL_PIN_MAP: string := "My_Pkg"); port (TDI_TDIC_AUX1 : inout bit; TDO_TDOC_AUX2 : inout bit; TMS_TMSC : inout bit; TCK_TCKC : in bit; nTRST_PD : in bit; GND : linkage bit_vector (1 to 2); VCC : linkage bit_vector (1 to 2); SYSCK : in bit; DQ : inout bit_vector (7 downto 0); NC : linkage bit_vector (1 to 2); ENA_STL : in bit; nDIS_STL : in bit; STRB : out bit; AB : out bit_vector (4 downto 0) ); use STD_1149_7_2009.all; use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE_ADAPTER of My_Dot7_IC : entity is "STD_1149_7_2009"; attribute COMPONENT_CONFORMANCE_STL of My_Dot7_IC : entity is "STD_1149_1_2001"; attribute PIN_MAP of My_Dot7_IC : entity is PHYSICAL_PIN_MAP; constant My_Pkg : PIN_MAP_STRING := "TDI_TDIC_AUX1 : 1," & "TDO_TDOC_AUX2 : 2," & "TMS_TMSC : 3," & "TCK_TCKC : 4," & "nTRST_PD : 5," & "GND : (6,21), VCC : (8,23)," & "SYSCK : 7," & "DQ : (9,10,11,12,17,18,19,20)," & "NC : (13,15)," & "ENA_STL : 14," & "nDIS_STL : 16," & "STRB : 22," & "AB : (28,27,26,25,24)"; attribute TAP_CLASS of My_Dot7_IC : entity is "T5W" attribute TAP_SCAN_CLOCK of TCK_TCKC : signal is (20.0e6, BOTH); attribute TAP_SCAN_MODE of TMS_TMSC: signal is true; attribute TAP_SCAN_IN of TDI_TDIC_AUX1 : signal is true; attribute TAP_SCAN_OUT of TDO_TDOC_AUX2: signal is true; attribute TAP_SCAN_CLOCK_COMPACT of TCK_TCKC : signal is ( 25.0e6, 35.0e6 ); attribute TAP_SCAN_MODE_COMPACT of TMS_TMSC: signal is true; attribute TAP_SCAN_IN_COMPACT of TDI_TDIC_AUX1 : signal is true; attribute TAP_SCAN_OUT_COMPACT of TDO_TDOC_AUX2: signal is true; attribute TAP_SCAN_RESET_PD of nTRST_PD : signal is true; attribute COMPLIANCE_PATTERNS_STL of My_Dot7_IC : entity is "( ENA_STL, nDIS_STL ) ( 11 )"; attribute INSTRUCTION_LENGTH of My_Dot7_IC : entity is 4; attribute INSTRUCTION_OPCODE of My_Dot7_IC : entity is "EXTEST (0011), " & "EXTEST (1011), " & "BYPASS (1111), " & "SAMPLE (0001, 1000), " & "PRELOAD(1001, 1000)," & "HIGHZ (0101), " & "CLAMP (0110), " & "IDCODE (1101), " & "USERCODE (1110), " & "SECRET (1010) "; attribute INSTRUCTION_CAPTURE of My_Dot7_IC : entity is "1X01"; attribute INSTRUCTION_PRIVATE of My_Dot7_IC : entity is "SECRET"; attribute IDCODE_REGISTER of My_Dot7_IC : entity is "00110010110011101001000010101001"; attribute USERCODE_REGISTER of My_Dot7_IC : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; attribute BOUNDARY_LENGTH of My_Dot7_IC : entity is 25; attribute BOUNDARY_REGISTER of My_Dot7_IC : entity is " 0 ( BC_1, SYSCK, input, X )," & " 1 ( BC_1, DQ(7), output3, X, 17, 1, Z )," & " 2 ( BC_1, DQ(7), input, X )," & " 3 ( BC_1, DQ(6), output3, X, 17, 1, Z )," & " 4 ( BC_1, DQ(6), input, X )," & " 5 ( BC_1, DQ(5), output3, X, 17, 1, Z )," & " 6 ( BC_1, DQ(5), input, X )," & " 7 ( BC_1, DQ(4), output3, X, 17, 1, Z )," & " 8 ( BC_1, DQ(4), input, X )," & " 9 ( BC_1, DQ(3), output3, X, 17, 1, Z )," & "10 ( BC_1, DQ(3), input, X )," & "11 ( BC_1, DQ(2), output3, X, 17, 1, Z )," & "12 ( BC_1, DQ(2), input, X )," & "13 ( BC_1, DQ(1), output3, X, 17, 1, Z )," & "14 ( BC_1, DQ(1), input, X )," & "15 ( BC_1, DQ(0), output3, X, 17, 1, Z )," & "16 ( BC_1, DQ(0), input, X )," & "17 ( BC_1, *, control, 1)," & "18 ( BC_1, STRB, output2, 1, 18, 1, WEAK1 )," & "19 ( BC_1, AB(0), output3, X, 24, 1, Z )," & "20 ( BC_1, AB(1), output3, X, 24, 1, Z )," & "21 ( BC_1, AB(2), output3, X, 24, 1, Z )," & "22 ( BC_1, AB(3), output3, X, 24, 1, Z )," & "23 ( BC_1, AB(4), output3, X, 24, 1, Z )," & "24 ( BC_1, *, control, 1 )"; attribute CNFG0_REGISTER of My_Dot7_IC : entity is "00011001111111111111111100010101"; attribute CNFG1_REGISTER of My_Dot7_IC : entity is "00000000000000000000000000001001"; attribute CNFG2_REGISTER of My_Dot7_IC : entity is "XXX0XXXXXXXXXXXXXXXXXXXXXXXXXXX1"; attribute CNFG3_REGISTER of My_Dot7_IC : entity is "XXXXXXXXXXXXXXXX1XXXXXXXXXXX0000"; end My_Dot7_IC; BSDL.7 example

56. BTW 2010 56 entity My_Dot7_module is generic (PHYSICAL_PIN_MAP: string := "My_PoP"); port (TDI_TDIC_AUX1 : inout bit; TDO_TDOC_AUX2 : inout bit; TMS_TMSC : inout bit; TCK_TCKC : in bit; nTRST_PD : in bit; GND_A : linkage bit_vector (1 to 2); VCC_A : linkage bit_vector (1 to 2); GND_B : linkage bit_vector (1 to 2); VCC_B : linkage bit_vector (1 to 2); SYSCK : in bit; DQ : inout bit_vector (7 downto 0); NC : linkage bit_vector (1 to 2); ENA_STL : in bit; nDIS_STL : in bit; STRB : out bit; AB : out bit_vector (4 downto 0) ); use STD_1149_7_2009_module.all; use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE_MODULE of My_Dot7_module : entity is "STD_1149_7_2009"; attribute PIN_MAP of My_Dot7_module : entity is PHYSICAL_PIN_MAP; constant My_PoP : PIN_MAP_STRING := "TDI_TDIC_AUX1 : 1," & "TDO_TDOC_AUX2 : 2," & "TMS_TMSC : 3," & "TCK_TCKC : 4," & "nTRST_PD : 5," & "GND_A : (6A,21A), VCC_A : (8A,23A)," & "GND_B : (6B,21B), VCC_B : (8B,23B)," & "SYSCK : 7," & "DQ : (9,10,11,12,17,18,19,20)," & "NC : (13,15)," & "ENA_STL : 14," & "nDIS_STL : 16," & "STRB : 22," & "AB : (28,27,26,25,24)"; attribute TAP_SCAN_CLOCK of TCK_TCKC : signal is (20.0e6, BOTH); attribute TAP_SCAN_MODE of TMS_TMSC: signal is true; attribute TAP_SCAN_IN of TDI_TDIC_AUX1 : signal is true; attribute TAP_SCAN_OUT of TDO_TDOC_AUX2: signal is true; attribute TAP_SCAN_CLOCK_COMPACT of TCK_TCKC : signal is ( 25.0e6, 35.0e6 ); attribute TAP_SCAN_MODE_COMPACT of TMS_TMSC: signal is true; attribute TAP_SCAN_IN_COMPACT of TDI_TDIC_AUX1 : signal is true; attribute TAP_SCAN_OUT_COMPACT of TDO_TDOC_AUX2: signal is true; attribute TAP_SCAN_RESET_PD of nTRST_PD : signal is true; -- Members Declaration attribute MEMBERS of My_Dot7_module : entity is "u1 (My_Dot7_IC, My_Pkg)," & "u2 (My_Dot7_IC, My_Pkg) " ; attribute MEMBERS_PORTMAP of My_Dot7_module : entity is "u1 (TDI_TDIC_AUX1 => TDI_TDIC_AUX1," & " TDO_TDOC_AUX2 => TDO_TDOC_AUX2," & " TMS_TMSC => TMS_TMSC," & " TCK_TCKC => TCK_TCKC," & " nTRST_PD => nTRST_PD," & " GND => GND_A," & " VCC => VCC_A," & " SYSCK => SYSCK," & " DQ => DQ, " & " ENA_STL => ENA_STL, " & " nDIS_STL => nDIS_STL," & " STRB => STRB," & " AB => AB), " & "u2 (TDI_TDIC_AUX1 => TDI_TDIC_AUX1, " TDO_TDOC_AUX2 => TDO_TDOC_AUX2," & " TMS_TMSC => TMS_TMSC," & " TCK_TCKC => TCK_TCKC," & " nTRST_PD => nTRST_PD," & " GND => GND_B," & " VCC => VCC_B," & " SYSCK => SYSCK," & " DQ => DQ, " & " ENA_STL => ENA_STL, " & " nDIS_STL => nDIS_STL," & " STRB => STRB," & " AB => AB)"; attribute MEMBERS_NODEIDS of My_Dot7_module : entity is "u1 (00010000)," & "u2 (00011000)"; end My_Dot7_module; HSDL.7 example