2. PLC Timer Instructions8
PLC Timer Instructions

3. Objectives
Use non-retentive and retentive timer ON-delay instructions to create PLC ladder logic diagrams.
Use move (MOV) instructions to create variable preset value timer instructions.
Use OFF-delay timers to create PLC ladder logic diagrams.
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4. Objectives Connect timer instructions to interlock each other.
Cascade timer instructions in a PLC ladder logic diagram to increase the timer preset values.
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5. Timers Fixed timers Variable timers Single-input timers
Double-input timers
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6. Timer Instructions
In the relay logic diagrams, symbols are used to represent timer coils and their associated timer contacts.
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7. Timer Instructions (Cont.)
Two types of timer instructions:
ON-delay timers.
OFF-delay timers.
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8. ON-delay Timers Start timing when timer coils are energized.
Normally open contacts close and normally closed contacts open when the timer is finished timing.
Contacts immediately revert to normal states when the timer accumulated register resets to zero.
Delay before contacts switch when timer turns on; no delay in switching when timer turns off.
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9. OFF-delay Timers Start timing when their timer coils are de-energized.
Normally open contacts close and normally closed contacts open when the timer is finished timing.
Contacts revert to their normal states when the timer accumulated register resets to zero.
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10. Timer Instruction Formats
Coil format:
Uses coils to display the timer instruction.
Block format:
Uses a box shape to display the timer instruction.
More common symbol for displaying timer instructions.
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11. PLC Timer Instruction Registers
Preset register:
Content is the preset value that the timer is initialized to hold.
Holds the preset number.
Accumulated register:
Holds the time that the timer has been timing.
Status register, also called flag register:
Holds the flag bits that are used by the PLC processor to monitor the status of the timer.
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12. PLC Timer Instruction Registers (Cont.)
Timers in Allen-Bradley SLC 500 series PLC:
Data file four (T4) reserved for timer instructions.
Timers have addresses T4:0 to T4:255.
In theory, can have up to 256 timers.
In practice, number of timers is limited by PLC memory capacity.
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13. Timer Base Number Multiplied by the preset number.
Defines unit of time as a fraction of a second or a second.
0.01 seconds, 0.1 seconds, and 1 second most commonly used in PLC timers.
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14. Timing Bits Enable bit (EN) Timer timing bit (TT) Done bit (DN)
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15. PLC Timer Instruction Timers
Three different types of timers for Allen-Bradley SLC 500 series PLCs:
Non-retentive timer ON-delay.
Retentive timer ON-delay.
Non-retentive timer OFF-delay.
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16. Fixed Preset Value Non-retentive Timer ON-Delay Instructions
Block diagram of an SLC 500 non-retentive timer ON-delay with address T4:0.
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17. Variable Preset Value Non-retentive Timer ON-Delay Instructions
Move (MOV) instruction:
Used for copying the content of one register into another or for loading a number into a register.
Can be used to create a variable preset timer.
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18. PLC Ladder Logic Diagram Using MOV and TON
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19. Retentive Timer ON-Delay Instructions
Reset (RES) instruction:
Used to reset a retentive timer.
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20. Timer OFF-Delay Instructions
PLC ladder logic diagram using timer off-delay.
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21. Interlocking Timers Interlocked timers:
Output turns on and off sequentially.
Common method of flashing lights or ringing bells in Allen-Bradley SLC 500 series programmable logic control systems.
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22. Interlocking Timers (Cont.)
PLC ladder logic diagram using two timers.
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23. Cascading Timers In some industrial applications:
Timers must have a large preset value.
PLC ladder diagrams that contain several timers can be created.
Cascading links multiple timers together.
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24. Cascading Timers (Cont.)
Timers are cascaded together such that when one timer is finished timing, the second one starts.
When the second timer is done, the third one starts, and so forth.
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25. PLC Ladder Logic Diagram Cascading Timers
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26. Glossary
Accumulated register: Register that holds the timer or counter accumulated value.
Block format: Format that uses a box shape to display the timer instruction.
Cascading: Arrangement of timer instructions in a ladder diagram that increases the number of counts or steps the instruction can achieve.
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27. Glossary
Coil format: Format that uses coils to display the timer instruction.
Data file four (T4): File that holds the timer registers.
Done bit (DN): Bit that is set when the instruction has completed its task, such as reaching its preset value or length value.
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28. Glossary
Double-input timer: Timer that uses one input to enable and another input to run.
Enable bit (EN): Bit that is set when the path of a rung is complete (all inputs are in the closed state).
Fixed timer: Timer that has a fixed preset value.
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29. Glossary
Interlocked timers: Timers used to turn an output on and off sequentially.
Move (MOV) instruction: Instruction that is used for copying the content of one register into another or for loading a number into a register. The move instruction can be used to create a variable preset timer.
Non-retentive timers: Timers that reset when they are de-energized.
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30. Glossary
OFF-delay timer: Timer that must be de-energized to start timing.
ON-delay timer: Timer that must be energized to start timing.
Preset register: Register that holds the timer or counter preset number.
Reset (RES) instruction: Instruction that must be used to reset the retentive timer.
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31. Glossary
Retentive timers: Timers that hold their accumulated value when they are disabled.
Single-input timer:Timer that has only one input for enable and run commands.
Status register: Register that holds the status bits. Also called flag register.
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32. Glossary
Timer base number: Number that must be multiplied by the timer preset number to generate the preset timer value.
Timer timing bit (TT): Bit that is energized when the timer is timing.
Variable timer: Timer that allows its preset value to be changed.
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