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High Level Languages: A Comparison By Joel Best
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2 Sources The Challenges of Synthesizing Hardware from C-Like Languages by Stephen A. Edwards High-Level Synthesis Fundamentals from "Low-Power High-Level Synthesis for Nanoscale CMOS Circuits" by Saraju P. Mohanty Synthesis from C in Electronic System Level (ESL) Design By Christopher Sullivan
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3 Overview Introduction to ESL High-level Synthesis Process C for Modeling Challenges and Solutions
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4 Electronic System Level Design Description of the system with a higher level of abstraction Necessary for complex SoCs Decreased development time Simulation is much easier
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5 The High-level Synthesis Process Compilation Transformation Allocation Binding Output generation
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6 The High-level Synthesis Process (cont’d) Compilation Behavior converted to internal representations Data flow graph (DFG) Control flow graph (CFG) Transformation DFGs and CFGs optimized and transformed Hardware optimizations such as associative and commutative operations
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7 The High-level Synthesis Process (cont’d) Scheduling and Resource Allocation Temporal partitioning of DFG and CFG to allow for concurrency Trade-offs such as area and timing accounted for Control steps needed and variable lifetimes determined
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8 Scheduling Algorithms Figure 1: Different types of scheduling algorithms (Mohanty, 2008)
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9 The High-level Synthesis Process (cont’d) Binding Functional unit binding Map an operation to a functional unit Memory unit binding Maps variables or constants to registers, RAM, or ROM Output Generation
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10 Using C for Hardware Familiar to many programmers Easier hardware/software co-design C-reference designs available for many applications Developed for von Neumann architecture Control unit, memory, ALU Fundamentally sequential
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11 C for Modeling Simulation is much faster at behavioral level than at the register-transfer level Transaction-level Modeling Separates functional units from communication Most parts not synthesizable SystemC most commonly used
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12 Sample Design Flow (SpecC)
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13 Challenges of using C Communication Concurrency Timing Data types Hardware control Pointers
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14 Communication Channels Channel data type for communication between parallel processes Receiver and transmitter must be ready at the same time (synchronization) Examples: Handel-C, HardwareC, Bach C
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15 Communication (cont’d) Multiple Primitives Channel can be a signal, buffer, FIFO, semaphore, mutex, etc Interfaces and ports for communication between functional units Events used for synchronization Examples: SpecC, SystemC
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16 Communication in SpecC interface I1 { bit[63:0] Read(void); void Write(bit[63:0]); }; channel C1 implements I1; behavior B1(in int, I1, out int); behavior B(in int p1, out int p2) { int v1; C1 c1; B1 b1(p1, c1, v1), b2(v1, c1, p2); void main(void) { par { b1.main(); b2.main(); } }; b1b2 v1 c1 B p1p2
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17 Concurrency Explicit Parallelism Which code is parallel and which is sequential specified by the programmer e.g. Handel-C Implicit Parallelism (SystemC) Similar to HDLs System describes processes which run in parallel
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18 Concurrency (cont’d) Compiler-identified Parallelism e.g. TransmogrifierC, CatapultC Good concurrent programming required Much different than software concurrency model
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19 SpecC Example (Explicit) behavior B_pipe { B b1, b2, b3; void main(void) {pipe{b1.main(); b2.main(); b3.main(); } } }; B_par b1 b3 b2 B_seq b1 b3 b2 B_fsm b1 b3 b2 b5b6 b4 B_pipe b1 b3 b2 behavior B_seq { B b1, b2, b3; void main(void) { b1.main(); b2.main(); b3.main(); } }; behavior B_fsm { B b1, b2, b3, b4, b5, b6; void main(void) { fsm { b1:{…} b2:{…} …} } }; behavior B_par { B b1, b2, b3; void main(void) { par{b1.main(); b2.main(); b3.main(); } } }; Sequential execution FSM execution Concurrent execution Pipelined execution Source: SpecC Lanugage Tutorial
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20 Timing Implicit rules for inserting clocks Handel-C Each assignment or delay is 1 clock cycle Channel communication is 1 clock cycle Transmogrifier C Each loop iteration and function call takes a cycle
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21 Timing (cont’d) Explicit clock definition (SystemC, Ocapi) For sequential logic, wait statements are used Combinational logic is implicit Clock constraint definition (HardwareC) Clock constraints for a particular section of code are specified
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22 Data Types No ANSI-C types smaller than a byte Actually… Compiler-driven data types Compiler chooses type size based on its use TransmogrifierC allows for preprocessor pragmas to specify integer width C2Verilog uses a GUI to set variable width
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23 Data Types (cont’d) Adding hardware types to C Allow specification of integer width Add boolean type E.g. Handel-C, Bach C, SpecC Using C++ types C++ type system allows for bit-level typing SystemC provides classes for variable-width integers and fractional numbers
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24 Hardware Control All languages differ in amount of control given over the hardware Handel-C Target FPGA specified for compilation Memory types such as RAM can be explicitly specified Macros provided for common operations
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25 Hardware Control (cont’d) SpecC: GUI used to specify how to translate certain constructs to hardware HardwareC Uses #pragmas within the code to specify timing or resource constraints
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26 Pointers Supported by Ocapi and SystemC and as long as the target is Synthesizable Compile-time determinable Not supported by Handel-C, TransmogrifierC, HardwareC, and most others Active area of research
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27 Conclusions Higher abstraction than RTL needed for complex system-on-chip systems C provides a proven foundation for behavioral description Most challenges can be overcome with a variety of methods
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Questions?
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29 RSA Encryption Progress Implementing 1024-bit co-processor Biggest challenge is implementing modular exponentiation in VHDL C=M e mod n Obtained reference design in C Using Montgomery’s method for modulus multiplication A*B mod n Much left to do…
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