Presentation is loading. Please wait.

Presentation is loading. Please wait.

Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University.

Published byRomeo Carey Modified over 9 years ago

Similar presentations

Presentation on theme: "Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University."— Presentation transcript:

1 Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University of Illinois at Chicago Sun Microsystems University of Illinois at Chicago

2 Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations, and future directions Acknowledgements

3 Motivation Traditional Flow Max Mode Optimization Logic Drops More Max Mode Optimization Close To Tape Out: Min Mode Analysis and Fixes Challenges: Resizing bits in banks? Repeater reposition? Room for more repeaters? Don’t aggravate critical paths!

4 Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations, and future directions Acknowledgements

5 Basic Algorithm in the Late Mode Try repeater sizes to generate solutions: (c, q) pairs Identify and prune sub-optimal; Merging @ fanout: avoid sub-optimal combinations Select the solution with highest q @ driver

6 Concurrent Min-Max Model q b close to q bd is better higher c helps to achieve q b closer to q bd (Note: initially q b  q bd ) if (c b1 (c b1, q b1 ) Objective Function: Late-Mode q w Constraint: Early-Mode Arrival Time at the Driver: q bd s 2 is sub-optimal compared to s 1 if (s 1 => s 2 ) s 2 is sub-optimal in late mode and s 2 is sub-optimal in early mode Solution: (c w, q w, c b, q b ) Late mode: s 1 => s 2 if (c w2 < c w1 ) and (q w2 < q w1 )

7 Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

8 Pruning a List of Solutions Four rules: c w2  c w1 in all cases: Case I: q b1 > q bd and q b2  q bd : Case II: q b1 > q bd and q b2 > q bd : Case III: q b1  q bd and q b2  q bd : Case IV: q b1  q bd and q b2 > q bd : s 2 cannot be pruned Prune s 1 if (c w1 = c w2 ) and (q w1  q w2 ) Prune s 2 if (q w2  q w1 ), (c b2  c b1 ) and (q b2  q b1 ) Prune s 1 if (q w1  q w2 ), (c w1 = c w2 ), (c b1  c b2 ), (q b1  q b2 ) Prune s 2 if (q w2  q w1 ) Prune s 1 if (c w1 = c w2 ), and (q w1  q w2 ) Prune s 2 if (q w2  q w1 )

9 Identifying sub-optimal solutions Solution c w q w 1 10100 2 11102 3 13101 4 15106 5 15105 6 16104 7 17103 8 18103 919109 10 20110 11 21108 12 22109 13 22111 14 23109 1524110 c b q b 550 651 652 752 854 955 655 854 1056 1157 1258 1359 1460 957 1156 Dominating Sol. 2 5 9

10 Complexity Reduction in Pruning sGPairSOAction 1ØNoneInsert 2{1}(1,2)Insert 3{1,2}(2,3)3Delete 4{1,2}NoneInsert 5{1,2,4}(4,5)Insert 6{1,2,5,4}(5,6) (4,6)Insert 7{1,2,6,5,4}(6,7)7Delete 8{1,2,6,5,4}(6,8) (5,8)8Delete

11 Further Reduction in Comparison Set Set G can be stored in a 2-Way binary tree: 1 st branch: q w 2 nd branch: q b 14G={1,2,6,5,4,11,9,12,10,13}(9,14)14Delete How to quickly identify the dominating solution 9 in group G?

12 Example Binary Tree Solution14: c w =23q w =109c b =9q b =57 Dominating Solution: 9: c w =19q w =109c b =10q b =56 G = {1,2,6,5,4,11,9,12,10,13} {1,2,6,5,4,11}{9,12,10,13} qwqw {9}{12,10,13} qbqb

13 Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

14 Merging Multiple Branches

15 Late Mode Merging LS = {(1,1)->(1X{2:3}), (2,2)->(2,3)}

16 Early Mode Merging ES = {(2,2)->(2X{1,3}), (1,2)->(1X{1,3})}

17 Identifying Non-Suboptimal Combinations LS = {(1,1)->(1X{2:3}), (2,2)->(2,3)} ES = {(2,2)->(2X{1,3}), (1,2)->(1X{1,3})} Sub-Optimal combinations are: (2,3) Non-suboptimal combinations: (1,2), (1,3), (2,1), and (1,1) Looking for a more efficient technique __________ _____

18 Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

19 Delay-Power Trade-Off How to avoid the flat region?

20 Techniques for Trade-Off John Lillis (ICCAD-95 ) Prune a solution if inferior in both p and q Algorithm highlights: Put solutions into power bins Intra-bin Pruning: Linear Inter-bin Pruning: more than linear Merging: all bin-pairs All trade-offs are explicitly computed and retained Final selections at the driver Issues: Large # of bins (esp. if slew dependent) Number of bin-pairs can be O(n 2 ) Large solution space => run time

21 Implicit Power-Delay Trade-Off Desired trade-off is captured in a parameter: =  delay/  power For example, if 0.01 ps delay reduction for a power dissipation of 1  w is acceptable, then = 0.01 ps/  w q a = q - *P (P = power/area); *P is a “penalty” Features:Trade-Off is Implicit Controlled Solution Space and Run Time Pruning a list: if (c 2  c 1 ) and (q 2a (c 2, q 2a ): Facilitates min-power solution (test nets) Merging Much detailed: could not include in this paper

22 Too Little to Gain @ Too Much Price Penalty#net buffered#repeaters 0.023045126 0.519282628

23 Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

24 Interaction Betwn. Late & Early Modes Caseq b1 (ps)q b2 (ps)Repeaters at Locations I1077132x at 3 and 7 II1287132x at 2 and 8; b mt at 5 III1288932x at 2, 16x at 8 and b mt at 5 IV12810132x at 2, 16x at 6 and 8, b mt at 5

25 Conclusion & Future Directions A new model for repeater insertion problem Early-mode timing requirement is a constraint Helps avoid aggressive late-mode optimization creating new early mode violations Should speed up design turn-around time by avoiding ECO’s to satisfy early-mode violations Techniques for satisfying maximum and minimum slew values, accurate timing to consider these slew values and avoid the flat region in the power-delay curve

26 Limitations & Future Directions Limitations Run time complexity Slack Budgeting Future research topics include: Combine gate sizing and repeater insertion Cone based Graph based Better merging techniques Controlling variations: process, voltage and temperature Hierarchical We welcome collaboration with academia

27 Acknowledgements Reviewers for detailed feedback Rob Mains for review & encouragements Aman Joshi and Sun Management for support Program Committee and the Organizers

28 Thank You

29 Satisfying Min-Max Slews

Download ppt "Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University."

Similar presentations

Porosity Aware Buffered Steiner Tree Construction C. Alpert G. Gandham S. Quay IBM Corp M. Hrkic Univ Illinois Chicago J. Hu Texas A&M Univ.

Porosity Aware Buffered Steiner Tree Construction C. Alpert G. Gandham S. Quay IBM Corp M. Hrkic Univ Illinois Chicago J. Hu Texas A&M Univ.
OCV-Aware Top-Level Clock Tree Optimization

OCV-Aware Top-Level Clock Tree Optimization
Mining Compressed Frequent- Pattern Sets Dong Xin, Jiawei Han, Xifeng Yan, Hong Cheng Department of Computer Science University of Illinois at Urbana-Champaign.

Mining Compressed Frequent- Pattern Sets Dong Xin, Jiawei Han, Xifeng Yan, Hong Cheng Department of Computer Science University of Illinois at Urbana-Champaign.
Advanced Interconnect Optimizations. Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 RAT = 300 Delay = 250 Slack.

Advanced Interconnect Optimizations. Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 RAT = 300 Delay = 250 Slack.
Buffer and FF Insertion Slides from Charles J. Alpert IBM Corp.

Buffer and FF Insertion Slides from Charles J. Alpert IBM Corp.
ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.

ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.
Timing Optimization. Optimization of Timing Three phases 1globally restructure to reduce the maximum level or longest path Ex: a ripple carry adder ==>

Timing Optimization. Optimization of Timing Three phases 1globally restructure to reduce the maximum level or longest path Ex: a ripple carry adder ==>
An Efficient Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints Rupesh S. Shelar Intel Corporation Hillsboro, OR 97124 Prashant.

An Efficient Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints Rupesh S. Shelar Intel Corporation Hillsboro, OR Prashant.
And Learning TEAL Consulting Limited a a Meeting Customer Demand in Challenging Times July 2010.

And Learning TEAL Consulting Limited a a Meeting Customer Demand in Challenging Times July 2010.
Chop-SPICE: An Efficient SPICE Simulation Technique For Buffered RC Trees Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of.

Chop-SPICE: An Efficient SPICE Simulation Technique For Buffered RC Trees Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of.
Current-Mode Multi-Channel Integrating ADC Electrical Engineering and Computer Science Advisor: Dr. Benjamin J. Blalock Neena Nambiar 16 st April 2009.

Current-Mode Multi-Channel Integrating ADC Electrical Engineering and Computer Science Advisor: Dr. Benjamin J. Blalock Neena Nambiar 16 st April 2009.
An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem Juyeon Kim, Deokjin Joo, Taehan Kim DAC’13.

An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem Juyeon Kim, Deokjin Joo, Taehan Kim DAC’13.
2015-6-11 Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.

Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.

TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.
Local Unidirectional Bias for Smooth Cutsize-delay Tradeoff in Performance-driven Partitioning Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts. Work supported.

Local Unidirectional Bias for Smooth Cutsize-delay Tradeoff in Performance-driven Partitioning Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts. Work supported.
Simulated-Annealing-Based Solution By Gonzalo Zea s031418 Shih-Fu Liu s031003.

Simulated-Annealing-Based Solution By Gonzalo Zea s Shih-Fu Liu s
Statistical timing and synthesis Chandu paper. Canonical form Compute max(A,B) = C in canonical form (assuming  X i independent)

Statistical timing and synthesis Chandu paper. Canonical form Compute max(A,B) = C in canonical form (assuming  X i independent)
Interconnect Optimizations

Interconnect Optimizations
On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield A. B. Kahng, B. Liu, X. Xu, J. Hu* and G. Venkataraman*

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield A. B. Kahng, B. Liu, X. Xu, J. Hu* and G. Venkataraman*

Similar presentations

Ads by Google