1. Enhanced SAR ADC Energy Efficiency from the Early Reset Merged Capacitor Switching Algorithm
Jon Guerber, Hariprasath Venkatram,
Taehwan Oh, Un-Ku Moon
Oregon State University, Corvallis OR, USA

2. EMCS SAR Switching Power EMCS Linearity Implementation Techniques
EMCS SAR Outline
MCS SAR Background
EMCS SAR Switching Power
EMCS Linearity
Implementation Techniques
Conclusions
Can explain all acronyms if desired. I didn’t add this outline slide anywhere else in the presentation since it was short, but you can if needed.

3. SAR Motivation SAR Contributions Current SAR Design Issues Low Power
Scalable
Low FOM even at small process nodes
Primarily dynamic power
I would explain FOM (as measure of overall SAR efficiency), mention that these design issues are only some of what comes up in design, but is what we will focus on with this work
Current SAR Design Issues
DAC takes a large portion of the SAR power budget
Without calibration DAC size (and power) is often based on mismatch concerns

4. Merged Capacitor Switching SAR
Merged Capacitor Switching (MCS)
Sampling reference is initially Vcm
Minimizes switching power by switching only once per phase
Maintains virtual node common mode
[1] [Hariprasath 2010]
[2] [Zhu 2010]
Feel free to add more details here when talking

5. MCS SAR Switching MCS Switching Differential
Each phase, current cap charges to VDD or GND
In the end, all caps have either VDD or GND on bottom plate
Switching energy based on code
I was going to use this slide to first explain how the MCS SAR switches (for a 1 code and 0 in multiple phases) and emphisise that the VCM code is not ever utilized in the final output digital word.

6. MCS SAR Switching

7. EMCS SAR Switching EMCS Switching Differential
Any {10} transition is replaced by {VCM,1}
Alternating code transitions have significantly lower energy
No extra switching events happen since all caps are reset eventually
Here I was going to highlight that all alternating transitions are replaced only in the 10 case (not 01) and that if the first bit is a “1” all the other bits will be a “1” or VCM (never a “0”)

8. EMCS SAR Switching

9. Switching Energy Comparison
EMCS Energy Savings
12.5% Lower energy over MCS
18.4% Lower energy over MCS when MCS is Gaussian distributed
41.5% Lower energy then set-and-down approach [3]
Even more energy savings is input PDF is concentrated in center
Here I would also mention that for input distributions that are typically small, the energy savings is larger. If people ask in the TSAR chip that DAC was over 40% of the total energy (probably 50% of that was drivers though)

10. EMCS Static Linearity MCS worst case DNL transition:
{1,0,0,0 …} to {0,1,1,1 …}
EMCS worst case DNL transition:
{1,VCM, VCM, VCM …} to {VCM,1,1,1 …}
and
{0,VCM, VCM, VCM …} to {VCM,0,0,0 …}
Variance of virtual ground node charge due to worst case code cap matching is ½
DNL reduced by factor of 2

11. EMCS Integral Non-Linearity
EMCS INL
INL reduced by factor of 2
Middle code is when all bits are VCM, hence INL = 0 there
INL Simulation performed with unit cap sigma of 0.02 LSB and 10,000 runs
Reduces size of a matching limited DAC, saves power
I would highlight that in mismatch limited SARs, the DAC size reduction reduces switching power by greater then 50%

12. EMCS Switching Algorithm
For (Stage = 1)
if Comp = 1
b1 = 1
else
b1 = 0
end
For (Stage = 2:End)
if CompN = b1
b(n) = b1
b(n-1) = VCM
EMCS Switching Algorithm
All final bits end up as either VCM or {b1}
In every phase, b(n) = b1
In each phase, comparator only dictates whether to reset capacitor b(n-1) or not

13. EMCS Logic Implementation
There are other implementations. Also I would emphasize that the AOI gate is extremely simple, (simpler then most other gates, esp XOR or OR) and that more logic minimization can be made with the latches. Also the last stage does not need an AOI gate.
EMCS Implementation
Efficient AOI gate resets data latches

14. EMCS SAR Summary Power Reduction Accuracy Improvements
Switching energy reduction without additional driver energy and minimal logic
Accuracy Improvements
Static linearity improvement, relaxed matching
Implementation Method
Low overhead implementation utilizing latch resetting

15. Questions

16. References
[1] V. Hariprasath, J. Guerber, S.-H. Lee, U. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, pp , Apr
[2] Y. Zhu, C.-H. Chan, U. Cho, S.-W. Sin, S.-P. U, R. Martins, F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp , Jun
[3] B. Ginsburg and A. Chandrakasen, “An energy efficient charge recycling approach for a SAR converter with capacitive DAC,” Proc. of IEEE Int. Sym. On Circuits and Systems, ISCAS, pp , 2005.