1. Chapter 1 : SystemC Overview

2. What is SystemC Systemc is a modeling platform  A set C++ class library to add hardware modeling constructs  Simulation kernel  Supports different levels of abstraction Untimed Functional Model Transaction Level Model Bus Function Model

3. Why we need systemc The increasingly shortened time to market requirements  Verify the design in early time The growing complexity  Integration of devise devices

4. SystemC Heritage ref : SOCLab 03_SOC_Design_Flow.pdf, 2004 spring, NCTU

5. SystemC Design Flow

6. Using software to simulate hardware behavior Extensions  Parallel execution  Clock  Module concept  Interconnection

7. Example – half adder #include “systemc.h” SC_MODULE(half_adder) { sc_in a, b; sc_out sum, carry; void proc_half_adder(); SC_CTOR(half_adder) { SC_METHOD (proc_half_adder); sensitive << a << b; } }; void half_adder::proc_half_adder() { sum = a ^ b; carry = a & b; }

8. Module --- Basic Block Verilog module module_name(input/output declaration) variable declaration computation block endmodule SystemC SC_MODULE (module_name) { input/output declaration internal variable constructor (computation block) };

9. Input/output Declaration Verilog  Input : input var1, …;  Output : output var2, …;  Type SystemC  input : sc_in var1, …;  Output : sc_out var2, …;  Type C++ primitive type : int, float, char,... hardware type : sc_int, sc_uint,... user defined type

10. Computation Block Verilog  Event trigger : always@(a or b or c)  Edge trigger : always@(posedge clk) SystemC SC_CTOR (module_name) { SC_METHOD (function name); sensitive << a << b << c; … } C++ constructor Sensitivity list Computation function name

11. Describing Hierarchy #include “half_adder.h” SC_MODULE (full_adder) { sc_in a, b, carry_in; sc_out sum, carry_out; sc_signal c1, s2, c2; void proc_or(); half_adder ha1(“ha1”), ha2(“ha2”); SC_CTOR(full_adder) { ha1.a(a); //by name connection ha1.b(b); ha1.sum(s1); ha1.carry(c1); h2(s1, carry_in, sum c2) //by position connection SC_METHOD (proc_or); seneitive << c1 << c2; } };

12. Main --- Top Module #Include “full_adder.h” #Include “pattern_gen.h” #include “monitor.h” int sc_main(int argc, char* argv[]) { sc_signal t_a, t_b, t_cin, t_sum, t_cout; full_adder f1(“Fulladder”); //connect using positional association f1 << t_a << t_b << t_cin << t_sum << t_cout; pattern_gen pg_ptr = new pattern_gen(“Genartion”); //connection using named association pg_ptr->d_a(t_a); pg_ptr->d_b(t_b); (*pg_ptr->d_cin(t_cin); monitor mol(“Monitor”); mo1 << t_a << t_b << t_cin << t_sum << t_cout; sc_start(100, SC_NS); return 0; }

13. SystemC Installation Download  http://twins.ee.nctu.edu.tw/courses/soc_sys_overview_04f all/lab/systemc-2.0.1.tgz  http://www.systemc.org Decompress data to /path/to/destination  C:\temp\ systemc-2.0.1\ Open project file  C:\temp\systemc-2.0.1\msvc60\systemc\systemc.dsw Build  Build->Build systemclib (F7)

14. Project compilation Example  http://twins.ee.nctu.edu.tw/courses/soc_sys_overview_04fall/lab/ systemc_ex01.rar http://twins.ee.nctu.edu.tw Decompression  C:\temp Create new project  File->New->Project->win32 Console application -> empty project Add existed files  Project->Add to Project -> Files  main.c module.c module.h Building argument and dependency  C++ runtime type indentification  Include path  Link path and libaray