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Example Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D0(R2), F0 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop.

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Presentation on theme: "Example Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D0(R2), F0 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop."— Presentation transcript:

1 Example Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D0(R2), F0 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop

2 Speculative Dynamic Machine specification Issue rate of 1 One broadcast per cycle for CDB branch takes 1 cycle, Load takes 1 cycle, integer alu takes 1 cycle, float add takes 2 cycle float multiply takes 3 cycle. These cycle count doesn’t include write to CDB

3 EntryBusyInstructionStateDestinationvalue 1N 2N 3N 4N 5N 6N 7N 8N 9N Reorder buffer NameBusyOPVjVkQjQkRob des Add1N Add2N Add3N Mult1N Mult2N Int1N Int2N Int3N Reservation table FieldF0f2 Reorder # Busynn FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle 0

4 EntryBusyInstructionStateDestinationvalue 1YLd f0, 0(R1)issuef0Mem(R1) 2N 3N 4N 5N 6N 7N 8N 9N Reorder buffer NameBusyOPVjVkQjQkRob des Add1N Add2N Add3N Mult1N Mult2N Int1YldR1#1 Int2N Int3N Reservation table FieldF0f2 Reorder ##1 BusyYn FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle 1

5 EntryBusyInstructionStateDestinationvalue 1YLd f0, 0(R1)executeF0Mem(R1) 2YAdd.d f0 f0, f2issueF0#1+F2 3N 4N 5N 6N 7N 8N 9N Reorder buffer NameBusyOPVjVkQjQkRob des Add1Yadddf2#1#2 Add2N Add3N Mult1N Mult2N Int1YldR1#1 Int2N Int3N Reservation table FieldF0f2 Reorder ##2 BusyYN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle 2

6 EntryBusyInstructionStateDestinationvalue 1YLd f0, 0(R1)WriteF0Mem(R1) 2YAdd.d f0 f0, f2ExcuteF0#1+F2 3Y S.D 0(R1), F0 issue 4N 5N 6N 7N 8N 9N Reorder buffer NameBusyOPVjVkQjQkRob des Add1Yadddf2#1#2 Add2N Add3N Mult1N Mult2N Int1YldR1#1 Int2YsdR1#2 Int3N Reservation table FieldF0f2 Reorder ##2 BusyYN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle 3

7 EntryBusyInstructionStateDestinationvalue 1NLd f0, 0(R1)commitF0Mem(R1) 2YAdd.d f0 f0, f2ExcuteF0#1+F2 3Y S.D 0(R1), F0 Excute 4Y L.D F0, 0(R2) IssueF0Mem(R2) 5N 6N 7N 8N 9N Reorder buffer NameBusyOPVjVkQjQkRob des Add1Yadddf0f2#2 Add2N Add3N Mult1N Mult2N Int1NldR1#1 Int2YsdR1#2 Int3YldR2#4 Reservation table FieldF0f2 Reorder ##4 BusyYN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle 4

8 EntryBusyInstructionStateDestinationvalue 1NLd f0, 0(R1)CommitF0Mem(R1) 2NAdd.d f0 f0, f2CommitF0#1+F2 3N S.D 0(R1), F0 Commit 4N L.D F0, 0(R2) CommitF0Mem(R2) 5Y Mult.D F0, F0, F2 WriteF0 6Y S.D 0(R2), F0 execute 7Y SUBI R1, R1, 8 ExecuteR1R1+8 8Y SUBI R2, R2, 8 executeR2R2+8 9YBnez r1, loopIssue Reorder buffer NameBusyOPVjVkQjQkRob des Add1N Add2N Add3N Mult1YMultdf0f2#5 Mult2N Int1Ysdr2#5#6 Int2YSubiR1#7 Int3Ysubir2#8 Reservation table FieldF0f2 Reorder ##5 BusyYN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle n

9 EntryBusyInstructionStateDestinationvalue 1NLd f0, 0(R1)issueF0Mem(R1) 2NAdd.d f0 f0, f2CommitF0#1+F2 3N S.D 0(R1), F0 Commit 4N L.D F0, 0(R2) CommitF0Mem(R2) 5N Mult.D F0, F0, F2 commitF0F0*F2 6Y S.D 0(R2), F0 execute 7Y SUBI R1, R1, 8 writeR1R1+8 8Y SUBI R2, R2, 8 executeR2R2+8 9YBnez r1, loopIssue Reorder buffer NameBusyOPVjVkQjQkRob des Add1N Add2N Add3N Mult1NMultdf0f2#5 Mult2N Int1Ysdr2f0#6 Int2YSubiR1#7 Int3Ysubir2#8 Reservation table FieldF0f2 Reorder # BusyNN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle n+1

10 EntryBusyInstructionStateDestinationvalue 1YLd f0, 0(R1)issueF0Mem(R1) 2NAdd.d f0 f0, f2CommitF0#1+F2 3N S.D 0(R1), F0 Commit 4N L.D F0, 0(R2) CommitF0Mem(R2) 5N Mult.D F0, F0, F2 commitF0F0*F2 6N S.D 0(R2), F0 commit 7Y SUBI R1, R1, 8 Done writeR1R1+8 8Y SUBI R2, R2, 8 writeR2R2+8 9YBnez r1, loopIssue Reorder buffer NameBusyOPVjVkQjQkRob des Add1N Add2N Add3N Mult1NMultdf0f2#5 Mult2N Int1Yldr1#1 Int2NSubiR1#7 Int3Ysubir2#8 Reservation table FieldF0f2 Reorder ##1 BusyYN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R2, Loop Cycle n+2

11 EntryBusyInstructionStateDestinationvalue 1YLd f0, 0(R1)issueF0Mem(R1) 2NAdd.d f0 f0, f2CommitF0#1+F2 3N S.D 0(R1), F0 Commit 4N L.D F0, 0(R2) CommitF0Mem(R2) 5N Mult.D F0, F0, F2 commitF0F0*F2 6N S.D 0(R2), F0 commit 7Y SUBI R1, R1, 8 ExecuteR1R1+8 8Y SUBI R2, R2, 8 executeR2R2+8 9YBnez r1, loopIssue Reorder buffer NameBusyOPVjVkQjQkRob des Add1N Add2N Add3N Mult1NMultdf0f2#5 Mult2N Int1Yldr1#1 Int2YSubiR1#7 Int3Ysubir2#8 Reservation table FieldF0f2 Reorder ##1 BusyYN FP register status Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D 0(R2), F0 SUBI R1, R1, 8 SUBI R2, R2, 8 BNEZ R1, Loop Cycle n+3

12 VLIW example Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D0(R2), F0 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop Static machine specification One delay slot between any true data flow dependency One branch delay slot

13 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F0, 0(R2) Mult.D F0, F0, F2 S.D0(R2), F0 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F1, 0(R2) Mult.D F1, F1, F2 S.D0(R2), F1 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop Register rename

14 Loop: L.D F0, 0(R1) Add.D F0, F0, F2 S.D 0(R1), F0 L.D F1, 0(R2) Mult.D F1, F1, F2 S.D0(R2), F1 SUBIR1, R1, 8 SUBIR2, R2, 8 BNEZR2, Loop Instruction reorder Loop: L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D0(R2), F1 SUBIR2, R2, 8 BNEZR2, Loop SUBIR1, R1, 8

15 Software pipeline L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D0(R2), F1 SUBIR2, R2, 8 SUBIR1, R1, 8 BNEZR2, Loop L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D0(R2), F1 SUBIR2, R2, 8 SUBIR1, R1, 8 BNEZR2, Loop L.D F0, 0(R1) L.D F1, 0(R2) Add.D F0, F0, F2 Mult.D F1, F1, F2 S.D 0(R1), F0 S.D0(R2), F1 SUBIR2, R2, 8 SUBIR1, R1, 8 BNEZR2, Loop 8 copies Code for one iteration.

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