1. Chapter 6 Multi-channel Buffered Serial Port (McBSP)

2. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.

3. Basic Definitions: Bits, Words ?
CLK FS
Data
Data a1 a0 b7 b6 b5 b4 b3 b2 b1 b0
Word
Bit
“Bit” - one data bit per SP clock period.
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Serial Port
“Word” or “channel” contains #bits specified by WDLEN1 (8, 12, 16, 20, 24, 32).
RWDLEN1 5 7
XWDLEN1

4. Basic Definitions: Frame?FS w0 w1 w2 w3 w4 w5 w6 w7
Frame
Word
Data
“Frame” - contains one or multiple words
FRLEN1 specifies #words per frame (1-128)
Serial Port
RFRLEN1 8 14
XFRLEN1 7 5
SP Ctrl (SPCR)
RWDLEN1
Rcv Ctrl (RCR)
Xmt Ctrl (XCR) 7 5
Rate (SRGR)
XWDLEN1
Pin Ctrl (PCR)

5. Basic Definitions - PhaseFS
Frame
Phase 1
Phase 2
Data A B 3 2 1
Note: dual-phase used in Audio Codec97 (AC97) Std
Each FRAME can contain only 1 or 2 PHASES (PHASE).
Each PHASE can contain different #bits (WDLEN1/2) and #words (FRLEN1/2) .
Phase 2
Phase 1
Serial Port
PHASE 31
RFRLEN2
RWDLEN2 23 24 21 30
XFRLEN2
XWDLEN2 14 8 7 5
SP Ctrl (SPCR)
RFRLEN1
RWDLEN1
Rcv Ctrl (RCR)
Xmt Ctrl (XCR) 14 8 7 5
Rate (SRGR)
XFRLEN1
XWDLEN1
Pin Ctrl (PCR)

6. Basic Definitions - PhaseFS 8 16
Data 1 2 3 A B
Phase 1
Phase 2
Frame
Each FRAME can contain 1 or 2 PHASES (PHASE).
Each PHASE can contain different #bits (WDLEN1/2) and #words (FRLEN1/2) .
From above example some of the bit fields of RCR and XCR can be initialised as shown below.
Phase 2
Phase 1
Serial Port 31 30 24 23 21 14 8 7 5
SP Ctrl (SPCR)
PHASE
RFRLEN2
RWDLEN2
RFRLEN1
RWDLEN1
Rcv Ctrl (RCR) 1
0001
010
0010
000
Xmt Ctrl (XCR) 31 30 24 23 21 14 8 7 5
Rate (SRGR)
PHASE
XFRLEN2
XWDLEN2
XFRLEN1
XWDLEN1
Pin Ctrl (PCR)

7. Exercise FS Data Phase 1 Phase 2 Frame16 20
Data 1 2 3 4 5 A B C
Phase 1
Phase 2
Frame
Fill in the control values for the example above.
RFRLEN2
PHASE
RWDLEN2
RFRLEN1
RWDLEN1 5 8 23 24 14 21 30 31 7
XFRLEN2
XWDLEN2
XFRLEN1
XWDLEN1
Phase 2
Phase 1

8. Definitions - Review CLK Word 1 Word 2 Word 3 FS Phase 1 Phase 2b1 b2
CLK
Word 1
Word 2
Word 3 FS
Phase 1
Phase 2
Phase 1
Phase 2
Frame 1
Frame 2
Serial Port
RFRLEN1
RWDLEN1 5 8 14 7
XFRLEN1
XWDLEN1
RFRLEN2
RWDLEN2 23 24 21 30
XFRLEN2
XWDLEN2 31
PHASE
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)

9. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.

10. McBSP Block Diagram (Read)
CPU
DMA
P e r i p h e r a l
B u s
RINT
REVT R B D 32 DR
CLKR
FSR
RSR

11. McBSP Block Diagram (Write)
CPU
DMA
RINT
XEVT
XINT
P e r i p h e r a l
B u s DR
CLKR
FSR
RSR R B D R 32 DX
XSR D X R
CLKX
REVT
FSX

12. McBSP Block Diagram (Configuration)
Multi-Channel Buffered Serial Port (McBSP)
CPU
DRR
P e r i p h
B u s DR
RSR
RBR DX
XSR
DXR
CLKR
Serial Port Control Logic
CLKX
DMA
RCR ?
FSR
SPCR
XCR ?
FSX
Peripheral Bus

13. Serial Port - Basic Operation
Multi-Channel Buffered Serial Port (McBSP)
CPU
DMA
DRR
P e r i p h
B u s DR
RSR
RBR DX
CLKX
FSX
XSR
DXR
CLKR
Peripheral Bus
Serial Port Control Logic
SPCR
RCR
XCR
PCR
SRGR
FSR
“TRANSMIT”
“RECEIVE”

14. McBSP Registers (1) Receive Transmit Control RSR Receive Shift Reg
RBR Receive Buffer Reg
DRR Data Receive Reg
Receive
XSR Transmit Shift Reg
DXR Data Transmit Reg
Transmit
SPCR Serial Port Control Reg
RCR Receive Control Reg
XCR Transmit Control Reg
Control

15. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.

16. Configure CLK and FS as inputs or outputs
Multi-Channel Buffered Serial Port (McBSP)
CLKR
Serial Port Control Logic
CLKX
RCR
SRGR
FSR
SPCR
FSX
XCR
PCR
FSR, FSX, CLKR and CLKX can be configured either as inputs or outputs, depending on the application.

17. Configure CLK and FS as inputs or outputs
Multi-Channel Buffered Serial Port (McBSP)
CLKR
Serial Port Control Logic
CLKX
RCR
SRGR
FSR
SPCR
FSX
XCR
PCR
CLK/FS Mode
0: Input
1: Output
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Serial Port 11 10 9 8
FSXM
FSRM
CLKXM
CLKRM

18. Generating CLK and FS as output
FSR
FSX
CLKR
CLKX
CLK/FS Mode
0: Input
1: Output
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Serial Port
CLKRM
FSRM 10
FSXM 11
CLKXM 8 9

19. Generating the CLK as output
Sample Rate Generator (SRGR)
CLKOUT1
CLKS
CLKGDV
CLKG
FSR
FSX
CLKR
CLKX
CLKSM
CLKSM - selects clock src (CLKOUT1 or CLKS)
CLKGDV - divide down (1-255)
CLKG = (input clock) / (1 + CLKGDV)
Max transfer rate = CLKG = 150 MHz/2 = 75 Mb/s
Serial Port
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
CLKSM 29
CLKGDV 7
Rate (SRGR)
Pin Ctrl (PCR)

20. Generating the FS as output
‘C6000
Sample Rate Generator (SRGR)
CLKSM
CLKOUT1
CLKS
CLKGDV
FSR
FSX
CLKR
CLKX
FPER
FSG
CLKG
FSGM: FS gen’d on every DXR XSR copy 1 - FS gen’d by FSG
FPER: frame sync period (12 bits)
Serial Port
SP Ctrl (SPCR)
FWID: frame sync pulse width (8 bits)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR) 29 28 27 16 15 8 7
Rate (SRGR)
CLKSM
FSGM
FPER
FWID
CLKGDV
Pin Ctrl (PCR)

21. McBSP Registers (2) Receive Transmit Control RSR Receive Shift Reg
RBR Receive Buffer Reg
DRR Data Receive Reg
Receive
XSR Transmit Shift Reg
DXR Data Transmit Reg
Transmit
SPCR Serial Port Control Reg
RCR Receive Control Reg
XCR Transmit Control Reg
SRGR Sample Rate Generator
Control

22. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port interrupts.
Describe multi-channel operation.
Programming the serial port.

23. Configure CLK and FS pin polarity
Multi-Channel Buffered Serial Port (McBSP)
CLKR
Serial Port Control Logic
CLKX
RCR
SRGR
FSR
SPCR
FSX
XCR
PCR
CLK/FS Polarity
0: Falling edge
1: Rising Edge
SP Ctrl (SPCR)
Rcv Ctrl (RCR)
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)
Serial Port 3 2 1
FSXP
FSRP
CLKXP
CLKRP

24. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port status and interrupts.
Describe multi-channel operation.
Programming the serial port.

25. RRDY/XRDY Status and Interrupts
RRDY/XRDY displays the “status” of the read and transmit ports:
0: not ready.
1: ready to read/write.
RBR
DRR
CPU
RINT
XINT
RRDY=1
“Ready to Read”
EDMA
Sync
There are 3 methods for detecting if data is ready:
Poll SPCR bits via s/w.
Config CPU ints (RINT/XINT).
Program DMA sync events.
XSR
DXR
XRDY=1
“Ready to Write”
Serial Port
SP Ctrl (SPCR) 17 1
Rcv Ctrl (RCR)
XRDY
RRDY
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)

26. Other sources of Interrupts (R/XINT)
RRDY (RINTM=00b)
End of Block (RCV) (RINTM=01)
New FSR (frame begin) (RINTM=10b)
Receive Sync Error (RINTM=11b)
XRDY (XINTM=00b)
End of Block (XMT) (XINTM=01b)
New FSX (frame begin) (XINTM=10b)
Transmit Sync Error (XINTM=11b)
“Trigger Event”
CPU
RINT
XINT
Serial Port
SP Ctrl (SPCR) 21 20 17 5 4 1
Rcv Ctrl (RCR)
XINTM
XRDY
RINTM
RRDY
Xmt Ctrl (XCR)
Rate (SRGR)
Pin Ctrl (PCR)

27. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port status and interrupts.
Describe multi-channel operation.
Programming the serial port.

28. Multi-Channel operation
DR/X
Ch0
Ch1
. . .
Ch31
Ch0
Ch1
. . .
Ch31
FSR/X
How do you enable/disable each channel?

29. Multi-Channel operation
DR/X
Ch0
Ch1
. . .
Ch31
Ch0
Ch1
. . .
Ch31
FSR/X
You can enable or disable any channel.
RCER/XCER Enable Bits
Enable [1] Disable [0] 31
Master (MCR)
Rcv En (RCER)
Xmt En (XCER)
Multi-Channel
RCER … 1 1 1 31
XCER

30. Multi-channel exampleF r a m e 4 3 2 1
Frame 3 1 4 3 2
Frame 2 1
Frame 1 4 3 2 3 1 3 1 M c B S P
Memory
Allows multiple channels (words) to be independently selected for transmit and receive. 1 3 .

31. Multi-channel and EDMA combination used for channel sorting
Memory 4 3 2 1
Frame 3 .
Frame 1
Frame 2 F r a m e M c B S P E D A
EDMA’s can sort each channel into separate buffers!

32. EDMA Channel Sorting 4 3 2 1 . Memory Frame 3 Frame 1 Frame 2 F r a mB S P E D A
EDMA’s flexible (indexed) addressing allows it to sort each channel into separate buffers!
How do you select channels? ...

33. Enable/Disable Channels
RCER / XCER registers allow you to enable or disable only 32-channels.
So how does the C6000 supports 128 channels? 31
RCER
XCER 1 …
Master (MCR)
Rcv En (RCER)
Xmt En (XCER)
Multi-Channel

34. 128 Channels!
0-15
16-31
32-47
48-63
64-79
80-95
96-111
Channels A B
To be able to support 128 channels the following applies:
Channels are broken into BLOCK’s (16 contiguous channels).
Up to 32 channels (2 BLOCK’s) can be enabled at any one time.
Channels are enabled via _CER registers and _BLK bits in MCR.
After 16 channels, McBSP issues END_OF_BLOCK interrupt.
CPU ISR re-programs RCER (or XCER) for channels and so on.
Interrupt
A15-0
B15-0 15 16
Master (MCR)
Rcv En (RCER)
Xmt En (XCER)
Multi-Channel 31
RCER
XCER

35. McBSP Registers (3) Receive Transmit Control RSR Receive Shift Reg
RBR Receive Buffer Reg
DRR Data Receive Reg
Receive
XSR Transmit Shift Reg
DXR Data Transmit Reg
Transmit
SPCR Serial Port Control Reg
RCR Receive Control Reg
XCR Transmit Control Reg
SRGR Sample Rate Generator
PCR Pin Control Reg
Control
MCR Multi-Channel Ctrl Reg
RCER Rcv Channel Enable Reg
XCER Xmit Channel Enable Reg

36. Objectives Definition of Terms:
Bit, word or channel, frame and phase.
Understand basic serial port operation.
Understand clock generation.
Pin polarity.
Serial port status and interrupts.
Describe multi-channel operation.
Programming the serial port.

37. Programming the Serial Port
There are three methods available for programming the serial port:
1. Writing directly to the serial port registers.
2. Using the Chip Support Library (CSL).
3. Graphically using the DSP/BIOS GUI configuration tool.

38. Programming the Serial Port - Direct
(A) Writing directly to the serial port registers:
Although this method is straight forward, it relies on a good understanding of the serial port functionality.
This method can be tedious and is prone to errors.
#include <c6211dsk.h>
void mcbsp0_init() {
*(unsigned volatile int *)McBSP0_SPCR = 0;
*(unsigned volatile int *)McBSP0_PCR = 0;
*(unsigned volatile int *)McBSP0_RCR = 0x10040;
*(unsigned volatile int *)McBSP0_XCR = 0x10040;
*(unsigned volatile int *)McBSP0_DXR = 0;
*(unsigned volatile int *)McBSP0_SPCR = 0x12001; }

39. Programming the Serial Port - CSL (1/4)
(B) Using the Chip Support Library:
The CSL provides a C language interface for configuring and controlling the on-chip peripherals, in this case the Serial Ports.
The library is modular with each module corresponding to a specific peripheral. This has the advantage of reducing the code size.
Some modules rely on other modules also being included, for example the IRQ module is required when using the EDMA module.

40. Programming the Serial Port - CSL (1/4)
CSL programming procedure:
(1) Create handles for the serial ports:
(2) Open the serial port:
MCBSP_Handle hMcbsp;
hMcbsp = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);

41. Programming the Serial Port - CSL (2/4)
CSL programming procedure:
(3) Create a configuration structure for serial port:
\Links\McBSP_Config_Struct.pdf

42. Programming the Serial Port - CSL (3/4)
CSL programming procedure (cont):
(4) Configure the serial port:
(5) Close the Serial Port after use:
MCBSP_config(hMcbsp,&ConfigLoopback);
MCBSP_close(hMcbsp);

43. Programming the Serial Port - CSL (4/4)
Practical example on DSP Code 6711
Project name: mcbsp_dynamiccfg.pjt
Location: \Code\Chapter 06 - McBSP\Dynamic_CSL_Config\

44. Programming the Serial Port using the DSP/BIOS GUI
(C) DSP/BIOS GUI Interface:
With this method the configuration structure is created graphically and the setup code is generated automatically.

45. Programming the Serial Port using the DSP/BIOS GUI
Procedure:
(1) Create a configuration using the MCBSP Configuration manager (eg. mcbspCfg0).

46. Programming the Serial Port using the DSP/BIOS GUI
Procedure:
(2) Right click on mcbspCfg0 and select “Properties”, see figures below, and then select “Advanced” and fill all parameters as shown below:

47. Programming the Serial Port using the DSP/BIOS GUI
Procedure:
(3) Select the serial port you would like to use from the MCBSP Resource manager (eg. Mcbsp_Port1).
Right click and select properties.
Select the mcbspCfg0 configuration just created.

48. Programming the Serial Port using the DSP/BIOS GUI
Procedure:
(4) A file is then generated that contains the configuration code. The file generated for this example is shown on the next slide.

49. Programming the Serial Port using the DSP/BIOS GUI
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten */
/* INPUT mcbsp1.cdb */
/* Include Header File */
#include "mcbsp1cfg.h"
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x , /* Serial Port Control Reg. (SPCR) */
0x000000A0, /* Receiver Control Reg. (RCR) */
0x000000A0, /* Transmitter Control Reg. (XCR) */
0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */
0x , /* Multichannel Control Reg. (MCR) */
0x , /* Receiver Channel Enable(RCER) */
0x , /* Transmitter Channel Enable(XCER) */
0x00000A /* Pin Control Reg. (PCR) */ };
/* Handles */
MCBSP_Handle hMcbsp1; /*
* ======== CSL_cfgInit() ======== */
void CSL_cfgInit() {
hMcbsp1 = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(hMcbsp1, &mcbspCfg0); }

50. Programming the Serial Port using the DSP/BIOS GUI
Few remarks:
(1) Notice that values in the code generated are the same as the values inserted using the GUI interface.
/* Do *not* directly modify this file. It was */
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x , /* Serial Port Control Reg. (SPCR) */
0x000000A0, /* Receiver Control Reg. (RCR) */
0x000000A0, /* Transmitter Control Reg. (XCR) */
0x203F1F0F, /* Sample-Rate Generator Reg. (SRGR) */
0x , /* Multichannel Control Reg. (MCR) */
0x , /* Receiver Channel Enable(RCER) */
0x , /* Transmitter Channel Enable(XCER) */
0x00000A /* Pin Control Reg. (PCR) */ };

51. Programming the Serial Port using the DSP/BIOS GUI
Few remarks:
(2) Do not forget to close the serial port after use.
(3) To visualise the output of the logprintf () function make sure that the Message Log window is open (DSP/BIOS > Message Log).

52. Programming the Serial Port - CSL (4/4) Practical example
Project name: mcbsp_staticcfg.pjt
Location: \Code\Chapter 06 - McBSP\Static_CSL_Config\
Extra Topic: Digital Loopback

53. Chapter 6 Multi-channel Buffered Serial Port (McBSP) - End -

54. Digital Loopback (DLB)
McBSP DR
CLKR
FSR
RCV
FSX
CLKX DX
XMT
Allows testing of the Serial Port code without the need of an external device.
Digital Loopback internally connects the rcv/xmt ports together as shown.
No hardware (pin connections) necessary.
Interrupts are generated as normal (as programmed).

55. Digital Loopback (DLB)
You can set the digital loop back by setting a bit in the SPCR or graphically using the GUI interface as shown:
SPCR 31 15
DLB