1. Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati

2. Programmable Interface device (Introduction) Requirement for programmable interface device Simple example configurable device Programmable Interface device 8155 – Block diagram – Address diagram – Interfacing LED using 8155 8155 Timer – Modes of timer – Square wave generation using 8155 interfaced timer Next class (8055 Handshake & Interrupt mode)

3. Designed to perform various I/O functions Device can be setup to perform specific functions – By writing instruction to a internal register Can be changed during execution of the program Devices are flexible, versatile & economical

4. Functions are determined by software instructions Can be viewed as multiple I/O device Perform many functions – Time delay, counting, interrupts Consists of many devices on a chip, interconnect through a common Bus Software programmable approach of I/O reduce design time

5. I/P & O/P Regs: A group of latches to hold data Tri-State Buffer Capability of Bidirectional data flow Handshake & Interrupt signal Control Logic Chip Select Logic Interrupt control logic

6. Configurable Device Example Latch Direction A B DirectionChip Select

7. Program MVIA,01 H ; Set Do=1, D1-D7==0 OUTFFH;Write in control register MVI A,BYTE1;Load data bye OUTFEH; Send Data out 7A 0A DIR G: Enable 7B 0B Control Reg Control Reg D0 D1 D7 A7 A6 A5 A4 A3 A2 A1 A0

8. 2kbits static RAM 256x8 2 programmable 8 bit I/O ports 1 programmable 6 bit I/O port 1 programmable 14 bit binary counter/timer Internal address latch to Demux AD0-AD7, using ALE line

9. RAM Port A Port A Port B Port B Port C Port C Timer MSB LSB Timer MSB LSB PA0-PA7 PB0-PB7 PC0-PC5 Timer Out Reset in RD WR ALE CE IO/M AD0-AD7 8155 Timer CLK

10. 3 to 8 Decoder CWR Port A Port A Port B Port B Port C Port C Timer MSB LSB Timer MSB LSB Latch Clock for timer PA0-PA7 PB0-PB7 PC0-PC5 Timer Out A0 A1 A2 ALE AD0-AD7 A0-A7 D7-D0 012345012345 CE b A2A1A0Port (ALE high, AD0=A0) 000Command /Status Register 001PA 010PB 011PC 100Timer LSB 101Timer MSB

11. 3 to 8 Decoder 3 to 8 Decoder 0404 A13 A12 A11 A15 A14 A2 A1 A0 5V 3 to 8 Decoder RAM Con trol CWR Port A Port A Port B Port B Port C Port C Timer MSB LSB Timer MSB LSB Latch Clock for timer PA0-PA7 PB0-PB7 PC0-PC5 Timer Out Reset in RD WR A0A0 A1A1 A2A2 ALE CE IO/M AD0-AD7 A0-A7 D7-D0 20H 21H 22H 23H 24H 25H CS

12. 3 to 8 Decoder RAM Con trol CWR Port A Port A Port B Port B Port C Port C Timer MSB LSB Timer MSB LSB Latch Clock for timer PA0-PA7 PB0-PB7 PC0-PC5 Timer Out Reset in RD WR A0 A1 A2 ALE CE IO/M AD0-AD7 A0-A7 D7-D0 8155 20H 21H 22H 23H 24H 25H

13. D0, D1: mode for PA and PB, 0=IN, 1=OUT D2, D3: mode for PC D4, D5: interrupt EN for PA and PB, 0=disable 1=enable D6, D7: Timer command: – 00: No effect – 01: Stop if running else no effect – 10: Stop after terminal count (TC) if running, else no effect – 11: Start if not running, reload at TC if running. Port C bits (D2, D3) D7D6D5D4D3D2D1D0 Timer CommandIEBIEAPCPBPA ALTD3D2PC5PC4PC3PC2PC1PC0 100IN 201OUT 310 STB A BF A INTR A 411STB B BF B INTR B STB A BF A INTR A

14. 8155 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 AD7 to AD0 IO/M b ALE RD b WR b RESET OUT IO/M b ALE RD b WR b RESET OUT 7 Seg LED Driver 7 Seg LED Driver 7 Seg LED Driver 7 Seg LED Driver 7 Seg LED Driver 7 Seg LED Driver 7 Seg LED Driver 7 Seg LED Driver 3 to 8 Decoder 3 to 8 Decoder 0404 A13 A12 A11 A15 A14 A2 A1 A0 5V

15. Port Address – Control Register=20H, Port A= 21H, Port B= 22H Control word: Program – MVIA,03 ; initialize Port A &B for O/P – OUT 20H – MVI A, BYTE1; Display BYTE1 at port A – OUT21H – MVIA, BYTE2; Display BYTE2 at port B – OUT22H D7D6D5D4D3D2D1D0 00000011 TimerNot Applicable Use for Port C Port B Output Port A Output

16. R S Gaonkar, “Microprocessor Architecture”, Chapter 14