1. SpecC and SpecCharts Reviewed and Presented by Heemin Park and Eric Kwan EE202A - Fall 2001 Professor Mani Srivastava

2. Overview Current problems in embedded systems development The solution – SpecC / SpecCharts Key feature: Program State Machine Highlight of SpecC Conclusion Questions

3. Current Design Problem Prototype debugging occupy 43% of development time Miscommunication of requirement Ambiguous specifications Absence of simulation and synthesis tool  HUGE design loop The reason – lack of a proper specification language Planning Specification Implementation Prototype Verification BIG LOOP!!

4. The solution: SpecC & SpecCharts Avoid miscommunication of requirement and incomplete / ambiguous specifications Proper specifications reduce debugging time by 29% Allow development of synthesis and simulation tools Simulate without building a prototype Planning Specification Implementation Prototype Performance Evaluation Rapid Prototyping AGILE DESIGN

5. Design Flow using SpecC Bus- functional Structural System design Specification model Algor. IP Proto. IP Architecture model Communication synthesis Communication model Comp. IP Implementation model Software compilation Interface synthesis Hardware synthesis Backend RTOS IP RTL IP Architecture exploration Capture Timed (estimated) RTL/IS Cycle- accurate Functional Structure / Implementation detail Untimed (causality) Order / Timing detail Timing- accurate SpecC

6. Properties of embedded System VHDL support the following behavior of embedded systems: Behavior Decomposition (Partial) Sequential Algorithm Behavior Completion (Partial) Not supported: State Transition Exceptions

7. Why did others failed? CharacteristicSpecChartsSpecCVHDLVerilogEsteral State Charts Behavioral decomposition Yes PartialYes State TransitionYes No Yes ExceptionYes NoYes Sequential algorithm Yes PartialNo Behavioral completion Yes PartialYes No

8. SpecCharts and SpecC Same Idea, different implementation SpecCharts is an extension to VHDL to tailored for embedded system design SpecC – ” specification description language based on C ” Both implement the idea of a Program State Machine (PSM)

9. Program State Machine(PSM) Hierarchical/Concurrent FSM + Programming language Program-state(PS) Status Inactive Executing Complete Computation Leaf Concurrent Sequential conditional transition arcs on completion or immediately

10. Program State Machine(Cont) SpecCharts PS described by procedures based on VHDL SpecC PS described by procedures in a programming language based on C PS4 PS5 PS3 PS2 PS1... a = 42; while (a<100) { b = b + a; if (b > 50) c = c + d; else c = c + e; a = c; }... PSM model Sequential Leaf Concurrent

11. SpecChart Descriptions Transition immediately(TI) (starts from boundary) Transition on Complete(TOC) Complete state behavior CheckCode type leaf is begin code_ok <= true; for (i in 1 to 4) loop wait until tone /= “1111” and tone’event; if (tone /= user_code(i)) then code_on <= false; end if; end loop; end; Textual-versionGraphical-version Initial state RemoteOperation code_ok=‘0’ hangup=‘1’ code_ok=‘1’ RespondToCmds CheckCode

12. Design Flow using SpecCharts VHDL Simulator SpecCharts to VHDL translator VHDL Synthesizer VHDL Verification tool VHDL Codes SpecChart Descriptions

13. The SpecC Model Traditional model Processes and signals Mixture of computation and communication Automatic replacement impossible SpecC model Behaviors and channels Separation of computation and communication Plug-and-play s2 s1 s3 P1P2 B2 v2 v1 v3 B1 C1

14. The SpecC Language ANSI-C Program is set of functions Execution starts from function main() SpecC Foundation: ANSI-C Program is set of behaviors, channels, and interfaces Execution starts from behavior Main.main() /* HelloWorld.c */ #include void main(void) { printf(“Hello World!\n”); } // HelloWorld.sc #include behavior Main { void main(void) { printf(“Hello World!\n”); } };

15. The SpecC Language Basic structure Top behavior Child behaviors Channels Interfaces Variables (wires) Ports b1b2 v1 c1 B p1p2 Behavior Ports Interfaces Channel Variable (wire) Child behaviors

16. The SpecC Language Basic structure interface I1 { bit[63:0] Read(void); void Write(bit[63:0]); }; channel C1 implements I1; behavior B1(in int, I1, out int); behavior B(in int p1, out int p2) { int v1; C1 c1; B1 b1(p1, c1, v1), b2(v1, c1, p2); void main(void) { par { b1.main(); b2.main(); } }; b1b2 v1 c1 B p1p2

17. behavior B_pipe { B b1, b2, b3; void main(void) {pipe{b1.main(); b2.main(); b3.main(); } } }; The SpecC Language Behavioral hierarchy B_par b1 b3 b2 B_seq b1 b3 b2 B_fsm b1 b3 b2 b5b6 b4 B_pipe b1 b3 b2 behavior B_seq { B b1, b2, b3; void main(void) { b1.main(); b2.main(); b3.main(); } }; behavior B_fsm { B b1, b2, b3, b4, b5, b6; void main(void) { fsm { b1:{…} b2:{…} …} } }; behavior B_par { B b1, b2, b3; void main(void) { par{b1.main(); b2.main(); b3.main(); } } }; Sequential execution FSM execution Concurrent execution Pipelined execution

18. Design Flow using SpecC Bus- functional Structural System design Specification model Algor. IP Proto. IP Architecture model Communication synthesis Communication model Comp. IP Implementation model Software compilation Interface synthesis Hardware synthesis Backend RTOS IP RTL IP Architecture exploration Capture Timed (estimated) RTL/IS Cycle- accurate Functional Structure / Implementation detail Untimed (causality) Order / Timing detail Timing- accurate SpecC

19. Conclusion SpecCharts PSM: model of computation for embedded system VHDL base: limited support for embedded software SpecC Well-known high-level language with support of PSM Design environment still developing Architecture exploration, refinement, communication synthesis,

20. Questions…

21. References Literature Vahid, F.; Narayan, S.; Gajski, D.D. SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. on CAD, Vol.14(No.6), June 1995. Pp.694- 706. SpecC: Specification Language and Methodology, by Gajski, Zhu, D ö mer, Gerstlauer, Zhao, Kluwer Academic Publishers, 2000. Circuits and Systems, 2001, Tutorial Guide: ISCAS 2001, The IEEE International The SpecC Language, pp.5.1_1-5.1_12. Modeling and Design with SpecC, pp.5.2_1-5.2_12. SpecC Design Environment, pp.5.6_1-5.6_4. SpecC Open Technology Consortium, pp.5.7_1-5.7_5. Online SpecC web pages at UCI http://www.cecs.uci.edu/~specc/ SpecC Open Technology Consortium (STOC) http://www.specc.org/ http://www.specc.org/