1. ASE Flip-Chip Build-up Substrate Design Rules
ADVANCED
SEMICONDUCTOR
ENGINEERING, INC.
ASE Flip-Chip
Build-up Substrate
Design Rules
Date : 2/12/2004 Rev. H

2. Content
 The Data needed for Design
 Build Up Flip Chip lead time
Flip Chip Pad Design Rule
Fine Flip Chip Pitch Proposal – 200 / 150 um
Layout Rule for Build Up Layer
Layout Rule for Core Layer
Available Substrate Structure
 Assembly Rule
 Substrate Roadmap

3. Design Information needed
 Package type & Body size
 Wafer thickness & Die size
Die orientation Including Pin 1 logo, die up or die down.
Die pad number, metal size & passivation opening.
UBM diameter
Solder bump height, pitch & composition.
 Solder ball size, pitch, number, location.
 Net list ( net name, coordinates and ball no. )
 Special Requirement (Thermal, Electrical or Others)

4. Build-Up Design Cycle-time & Delivery
Flip Chip BGA days >>> days
Built-up Substrate 1st Article Delivery:
(After Vendor drawing confirm)
Lead Time General Hot-Run
1+2+1 layers : wk wk
2+2+2 layers : wk wk
3+2+3 layers : wk wk
4+2+4 layers : wk wk
For ASEMT Only:
Lead Time General Hot-Run *Super Hot-Run
1+2+1 layers : wk 3.5 wk wk
2+2+2 layers : wk wk wk
3+2+3 layers : wk wk wk
4+2+4 layers : wk wk wk
* Maximum 1K units (per substrate per order)

5. Flip Chip Pad Design Rule
SMD with Solder
Bump on Via (Filled)
Solder
Resist
Bump 1 3 2
Solder
Resist
Bump 1 3 2
< Unit : um > #
Item
Normal
Advance
Risk 1
Min. Solder resist opening
100 90 85 2
Min. S/M Coverage 25 20 15
C4 pad pitch ( no line pass ) 3
180
155
150
C4 pad pitch ( pass one lines )
Trace on neck 25 um
225
200
175

6. Proposal for fine flip chip pitch-I
**200 um Bump Pitch for One Line Pass
Solder
Resist
Bump B A C F G

7. Proposal for fine flip chip pitch-II
**150 um Bump Pitch for One Line Pass
Solder
Bump B A
Solder
Resist C E
1st layer F D H
2nd layer G
For 150um proposal, Need to Control Die Bump UBM Diameter: 70 ~ 90 um

8. Layout Rule for Build Up LayerC D E G H
Bump Local Area F

9. Layout Rule for Core LayerB D F B A

10. Substrate Structure Layer Number Layer Structure Core layer Ni Plating
Au Plating
Build up layer
Solder resist
Solder
Number of
build up layer
1, 2, 3, 4 / Side
2, 4
Core layer
Layer Structure
Location
Thickness ( um )
Core substrate
800
Core Cu 29
Build up Cu 15
Insulation layer 34
Solder Resist layer 24
Nickel plating
3~7
Gold plating (Immersion Gold)
0.03~0.12

11. Assembly Rule Chip Capacitor Rule
UNIT: um
0402 A B C
G(min) C A B G
Pad
450
400
600
500
0603 A B C
G(min)
Pad
800
700
900
750
0612 A B C
G(min)
Pad
510
830
3450
1000
0306 A B C
G(min)
Pad
380
340
1730
750

12. Peripheral bump allocation
FC CSP E F
Die B
Die D C A
Peripheral bump allocation
Array bump allocation
Unit : mm
Dimension
Item
Desicription
Remark
Over molded FC CSP
Underfilled FC CSP A
Package size
4≦ A, B≦ 15
4 ≦A, B≦ 15
14x22 is Max. rectangular package size B C
≦ (A-2)
≦ (A-3)
Die size D
≦ (B-2)
≦ (B-3) E
Bump pitch
0.25 min.
0.25 min.
By peripheral for substrate design F
Bump pitch
0.25 min.
0.25 min.
By array for substrate design
Notes: * If it is array bump placement for Over molded FC CSP, there is a limitation for no bumps by 2x2mm area in the center of die.
** The bump pitch 315 um min. should be regarded with substrate C4 pads design. For routing concern, the design of bump pitch should be larger than 315 um for layout routing.

13. FCBGA Die on the top Die on the bottom A B G1 H1 G2 H2 Chip Capacitor
Attached Area.
Die on the bottom A B G H
To achieve our mission, we have the following strategies:
We will locate our main facilities in IC clusters with foundries to provide clients complete solutions in IC outsourcing.
This also allows us to work closely with front-end service providers to develop technology and processes for the next generation of products.
We will continue to grow organically as well as through strategic acquisitions.
We will maintain and further enhance our leadership in offering complete semiconductor manufacturing services through technology driven solutions.
We will leverage our dominance in test as it is increasingly becoming a key differentiator.
Also, we will be aggressively ramping up our capacity in design and production of substrates, which are becoming a significant percentage of packaging costs and are currently controlled by a limited number of vendors.

14. HFC BGA Two-piece Metal Two-piece Metal Once-piece MetalD E B C F
Stiffener Ring A F E D C
Chip Capacitor
Attached Area.
Once-piece Metal
One-piece Metal
To achieve our mission, we have the following strategies:
We will locate our main facilities in IC clusters with foundries to provide clients complete solutions in IC outsourcing.
This also allows us to work closely with front-end service providers to develop technology and processes for the next generation of products.
We will continue to grow organically as well as through strategic acquisitions.
We will maintain and further enhance our leadership in offering complete semiconductor manufacturing services through technology driven solutions.
We will leverage our dominance in test as it is increasingly becoming a key differentiator.
Also, we will be aggressively ramping up our capacity in design and production of substrates, which are becoming a significant percentage of packaging costs and are currently controlled by a limited number of vendors. B
0.80
1.45

15. Multi-Chip Module MCM / FCBGA MCM / HFCBGA Chip Cap Attached Area. G1
Cx1
Dy1
Dx1
Cy1
Cx3
Dy3
Dx3
Cy3
Cx2
Dy2
Dx2
Cy2 E
To achieve our mission, we have the following strategies:
We will locate our main facilities in IC clusters with foundries to provide clients complete solutions in IC outsourcing.
This also allows us to work closely with front-end service providers to develop technology and processes for the next generation of products.
We will continue to grow organically as well as through strategic acquisitions.
We will maintain and further enhance our leadership in offering complete semiconductor manufacturing services through technology driven solutions.
We will leverage our dominance in test as it is increasingly becoming a key differentiator.
Also, we will be aggressively ramping up our capacity in design and production of substrates, which are becoming a significant percentage of packaging costs and are currently controlled by a limited number of vendors.

16. Fiducial Mark Rule - 1
1. Fiducial Mark Of Flip Chip Process (exposed size)
Unit : um
SPEC
TYP.
SPECIAL
FIGURE
DESCRIPTION
(min)
(min)
REMARK
Distance between die edge
corner to the center of
fiducial mark for adding
spreader
Could be even
smaller if there is A
3000
2200
No heat spreader
requirement A
If there were SMD B
Diameter of Circle Mark
500
380
component, Special
rule can’t apply.
If there were SMD C
Width of square mark
500
380
component, Special B C
rule can’t apply. B D
If there were SMD D
Length of square mark
500
380
component, Special
rule can’t apply.
Notes: ●
   
Each substrate should have more than two fiducial marks for flip chip process. ●
   
Fiducial mark should be put on the outer side's of die edge corner 3 mm min. ●
   
All the fiducial marks should be put on the diagonal location,
and there must be two different fiducial mark on the diagonal location.

17. Fiducial Mark Rule - 2 FIGURE DESCRIPTION For NSMD type C4 Pad A
2. Solder Mask Opening for fiducial mark
Unit : um
SPEC.
FIGURE
DESCRIPTION
TYP.
SPECIAL
REMARK
(min)
(min)
For NSMD type C4 Pad A
Distance of S/M to
fiducial mark 50 -- C A B
Distance of S/M to
fiducial mark B 50 --
Distance of S/M to
fiducial mark C 50 --
Solder mask opening
For SMD (with solder) type C4 Pad
Distance of S/M to
fiducial mark A 50 -- C A B
Distance of S/M to
fiducial mark B 50 --
Distance of S/M to
fiducial mark C 50 --
Solder mask opening

18. New Via Structure Time Line-I

19. New Via Structure Time Line-II