1. Ngwe Soe Zin, Andrew Blakers Australian National University Centre of Sustainable Energy System Evan Franklin, Vernie Everett

2.  Purpose of the work  Background of the Project  Silicon Solar Cells for VHESC program Cell Design Design Considerations Target Efficiency Modelling and Characterisation Metal Plating IV Test Data Characterisation of Recombination Conclusion

3.  Ultra-High efficiency solar cell devices are a major step forward in the development of low- cost PV technology  Commercial applications, energy security, green house gas reductions, industry development  Military applications, pollution reduction  Potential trigger to revolutionise global electricity generation

4.  Solar cell efficiencies are approaching their practical efficiency limits  Single junction: 25% eff. in Si or GaAs (85% of practical efficiency)  Tandem: 38% for 3-stack under concentration (70% of practical efficiency)

5.  Very High Efficiency Solar Cell (VHESC) program works towards six-junction tandem solar cell stack approach  VHESC integrates optics, interconnects, and cell designs  Benefits:  Increased “design space”  Increased theoretical efficiency  Introduces options for new architectures  Greater device design flexibility  Reduced spectral mismatch losses  Increased materials choices  VHESC cells will be used in the mobile battery charging application

6. High Eg 2.40 eV GaInP 1.80 eV GaAs 1.43 eV Si 1.12 eV 0.95 eV 0.70 eV 14.9% 16.6% 13.9% 9.7% 5.0% 4.1% 13.8% 14.3% 11.7% 7.8% 3.8% 2.9% 13.8% 14.3% 12.0% 8.5% 4.0% 3.0% 6J Solar Cell Band Gap Thermodynam ic Efficiency Practical Efficiency Limit 6-junction Solar Cell at 20 X 100 X Total η = 64.2% Total η = 54.3% Total η = 55.6%  IEEE Barnett et al 2006 Derating of thermodynamic efficiency

7. 2.5 mm 0.3 mm 0.15 mm 0.5 mm 5.5 mm 0.75 mm 6.5 mm 1.9 mm 0.3 mm Emitter Region (n+) Base Region (p) Metal Contact Bifacial Cell N Contact at the Front P Contact at the Back

8. 1.Illumination Light of energy <1.42eV to Silicon Light of energy <1.1eV to underlying cells BSR not an option Cell thickness should be 0.5-2mm for reasonable conversion efficiency for 875-1100nm 2.Recombination Thermal oxidation for Surface Recombination Cutting cells individually from the host wafer for Edge Recombination Contact is <1% of total surface area for Contact Recombination 3.Anti-Reflection Optimisation of oxide and nitride thickness to reduce reflection loss of i.1% in air ii.3% under encapsulation 4.IQE Diffusion length >> Cell thickness for more than 90% IQE 5.Resistive Losses 500µm thick cell will absorb 87% of the light (875-1100nm) in the top half of the cell Current sharing in bifacial cell will minimise resistive losses partially Electron current at the rear of diffused emitter will be small 6.Lateral Diffusive Losses Electron resistive loss is more concerned than that of hole since Rs of 500µm 1Ωcm << Rs of Emitter Diffusion For estimated resistive loss of <5%, n++ contacts will be at both edges and ends of the cell (similar configuration for p++ contacts)

9. 1.9mm - + GaInP/GaAs High Eg Cell Silicon Input Power Before Silicon Material (875-1100nm) = Target Efficiency = = 5.2% = Output Power of Cell Isc x Voc x FF = = 6mA x 630mV x 78% Input Power Before High Band-Gap Materials

10. Main Parameters Used for Modelling Active Area for 15mm Illumination at 1 sun intensity Bifacial Emitter as Active Region Heavy Phosphorous and Boron Diffusions IscVocIQE (800-1000nm) 4.17mA630mVup to 90%

11.  QSSPC technique was used to characterise effective carrier lifetime and emitter saturation current.  Carrier lifetime after all high temperature step was maintained at around 560µs (~ implied-Voc of 640mV)  Surface recombination was also remained low at around 25 fA/sq cm

12.  metallisation of small contact with dimension of 200µm x 5.5mm  evaporated metal contacting method needs  Fabrication of selective mask with opening only to contacts can tedious  Alignment of mask to contact can be error-prone  Misalignment can cause shading loss and shunting

13.  Light-induced plating for n++ contacts  Electrolyte plating for p+ contacts  Both plating performed concurrently

14. Optical Microscope Measurement n++ Contact p+ Contact Light-Induced Plating ~1µm/min at 120V Electrolyte~1µm/min for 0.05A and 0.03V Assuming the conditions: Current generated by light enters in the emitter equally Current enters the metal bus bar from one end and extracted from the other end Power Loss (%) AFM Rate of Plating

15. Silicon Etch Laser Scribe TMAH EtchRCA Clean LPCVD Si Etch for n+ Si SiN n+ Diffusion n+ Strip SiN n+ Oxidation & LPCVD n+ Etch for n++ n+ Diffusion n+ Oxidation n+ Etch for p+ n+ Diffusion n+ Oxide Removal Metallisation n+ Dicing

16. I-V Testing IntensityVoc(mV)Isc(mA)FF (%) Cell015653.470 Cell025663.3675 Cell055693.3879  Tested by flash-tester under 1 sun illumination  Demonstrates the absence of shunt and good fill-factor  Low Voc and Isc could be due to recombination at the emitter and cell edge (cells diced out of host wafer)  Recombination due to cell edge unlikely since active region is at least 1mm away from cell edge

17. Characterisation  Recombination at the emitter region is suspected  Experiment on dielectric using as etch mask and diffusion barrier 1st Group of Wafer2nd Group of Wafer 1Grow NitrideGrow Oxide 2Measure Lifetime 3Strip Nitride in HFStrip Oxide in HF 4 Cleaved Wafers 5Diffusion 6Grow Oxide 7Grow Nitride 8Measure Lifetime

18. Characterisation 1st Group of Wafer 1Grow Oxide 2Measure Lifetime 3RIE 4 Cleaved Wafers 5Diffusion 6Grow Oxide 7Grow Nitride 8Measure Lifetime  Experiment on dry etching (RIE) if it has impact on lifetime  Results were compared against the earlier results

19. Characterisation  Samples deposited with nitride as etch mask or diffusion mask results in low lifetime compared to oxide  Implied Voc was also observed lower for Sample using nitride as a etch mask  Using nitride directly on top of silicon as etch mask or diffusion barrier may induce stress and thermal mismatch  Samples etched by RIE to form emitter region has suffered drastic lifetime loss among all samples  Ion damage caused by RIE on the silicon causes lifetime loss significantly

20.  Cells fabricated present the absence of shunting and good fill-factor  Low Voc and Isc for cells  Possible factors causing low Voc and Isc were identified  Subsequent batch of cell fabrication could increase the cell efficiency sharply Conclusion