1. EKT 124 / 3 DIGITAL ELEKTRONIC 1
CHAPTER 3
Counters (cont.)

2. Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip-flops.
1. State Diagram

3. 2. Next-state table
Present State
Next State Q2 Q1 Q0 1

4. Transition Table for a J-K flip-flop
Output Transitions
Flip-flop Inputs QN
QN+1 J K  X 1

5. 3.K-Map

6. 4.The Counter Circuit

7. Example: State diagram for a 3-bit up/down Gray code counter.

8. The 74HC163 4-bit synchronous binary counter
The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

9. Timing example for a 74HC163.

10. The 74LS160 synchronous BCD decade counter
The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

11. Timing example for a 74LS160.

12. UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

13. Timing Diagram

14. The 74HC190 up/down synchronous decade counter.

15. Timing example for a 74HC190.

16. J and K maps - The UP/DOWN control input, Y, is treated as a fourth variable.

17. Three-bit up/down Gray code counter