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FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n 16 x 16 multiplier example.

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Presentation on theme: "FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n 16 x 16 multiplier example."— Presentation transcript:

1 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n 16 x 16 multiplier example.

2 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR The FPGA design process n Translation from HDL. –(synthesis, translation) n Logic synthesis. –(mapping) n Placement and routing. –(place and route) n Configuration generation. –(program file generation)

3 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Design experiments n Synthesize with no constraints. n Synthesize with timing constraint. –Tighten timing constraint. n Synthesize with placement constraints.

4 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Post-translation simulation model n HDL model in terms of FPGA primitives. n Example: X_LUT4 \p12_Madd__n0015_Mxor_Result_Xo 1 (.ADR0(x_7_IBUF),.ADR1(y_13_IBUF),.ADR2(c12[7]),.ADR3(row12[8]),.O(row13[7]) );

5 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Mapping report Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 501 out of 1,024 48% Logic Distribution: Number of occupied Slices: 255 out of 512 49% Number of Slices containing only related logic: 255 out of 255 100% Number of Slices containing unrelated logic: 0 out of 255 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 501 out of 1,024 48% Number of bonded IOBs: 64 out of 92 69% Total equivalent gate count for design: 3,006 Additional JTAG gate count for IOBs: 3,072 Peak Memory Usage: 64 MB

6 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Static timing analysis report Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 99.999 uS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 20.916ns. --------------------------------------------------------------- -----------------

7 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Static timing report: delays along paths Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Pad to Pad ------------------+----------------------+-----------+ Source Pad |Destination Pad| Delay | ------------------+----------------------+-----------+ x |p | 5.824| x |p | 10.675| x |p | 11.214| x |p | 11.753|

8 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Routing report Phase 1: 1975 unrouted; REAL time: 11 secs Phase 2: 1975 unrouted; REAL time: 11 secs Phase 3: 619 unrouted; REAL time: 12 secs Phase 4: 619 unrouted; (0) REAL time: 12 secs Phase 5: 619 unrouted; (0) REAL time: 12 secs Phase 6: 619 unrouted; (0) REAL time: 12 secs Phase 7: 0 unrouted; (0) REAL time: 12 secs The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

9 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Static timing after routing Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 99.999 uS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 38.424ns. --------------------------------------------------------------- -----------------

10 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Timing constraint n Use timing constraint editor:

11 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Post-map static timing report Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 20.916ns.

12 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Post-routing static timing report Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ; 20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 31.984ns.

13 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Tighter timing constraints n Tighten requirement to 25 ns. n Post-place-route timing report: Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 25 nS ; 20135312 items analyzed, 11 timing errors detected. (11 setup errors, 0 hold errors) Maximum delay is 31.128ns.

14 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Report on a violated path Slack: -6.128ns (requirement - data path) Source: y (PAD) Destination: p (PAD) Requirement: 25.000ns Data Path Delay: 31.128ns (Levels of Logic = 31) Data Path: y to p Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K5.I Tiopi 0.825 y y y_0_IBUF SLICE_X2Y11.G4 net (fanout=31) 1.792 y_0_IBUF SLICE_X2Y11.Y Tilo 0.439 c2 p0_Madd__n0017_Mxor_Result_Xo 1 SLICE_X2Y11.F4 net (fanout=2) 0.304 row1 SLICE_X2Y11.X Tilo 0.439 c2 p1_Madd__n0019_Cout1 SLICE_X5Y16.F3 net (fanout=2) 0.784 c2 SLICE_X5Y16.X Tilo 0.439 c3 p2_Madd__n0019_Cout1 SLICE_X2Y18.G4 net (fanout=2) 0.668 c3 SLICE_X2Y18.Y Tilo 0.439 row5 p3_Madd__n0019_Mxor_Result_Xo 1

15 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Power report Power summary: I(mA) P(mW) ---------------------------------------------------------------- Total estimated power consumption: 333 --- Vccint 1.50V: 0 0 Vccaux 3.30V: 100 330 Vcco33 3.30V: 1 3 --- Inputs: 0 0 Logic: 0 0 Outputs: Vcco33 0 0 Signals: 0 0 --- Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3 Thermal summary: ---------------------------------------------------------------- Estimated junction temperature: 36C Ambient temp: 25C Case temp: 35C Theta J-A: 34C/W

16 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Power report: decoupling capacitance Decoupling Network Summary: Cap Range (uF) # ---------------------------------------------------------------- Capacitor Recommendations: Total for Vccint : 4 470.0 - 1000.0 : 1 0.0100 - 0.0470 : 1 0.0010 - 0.0047 : 2 --- Total for Vccaux : 4 470.0 - 1000.0 : 1 0.0100 - 0.0470 : 1 0.0010 - 0.0047 : 2 --- Total for Vcco33 : 10 470.0 - 1000.0 : 1 0.470 - 2.200 : 1 0.0470 - 0.2200 : 2 0.0100 - 0.0470 : 3 0.0010 - 0.0047 : 3

17 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Improving area n Floorplanner window: LEs Chip floorplan

18 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Rat’s nest wiring

19 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Routing editor view

20 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Adding placement constraints n Must add attributes to the Verilog: // synthesis attribute rloc of p0 is X0Y0 multrow p0(row0,x,y[1],y[0],c0,row1,c1);

21 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Editing constraints n Use constraints editor to place constraints:

22 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Design browser pane

23 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Drag and drop constraints

24 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Change the shape of constraints

25 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Full set of placement constraints

26 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Placement results

27 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR New timing report n After placement constraints: 19742142 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 29.934ns. n Compares to 31 ns for unconstrained placement.

28 FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Detailed routing constraints

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