1. Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems Érika Cota Luigi Carro Flávio WagnerMarcelo Lubaszewski UFRGS Porto Alegre, Brazil

2. b a c kn e x th o m e Context SoC core

3. b a c kn e x th o m e Reuse Model tester SoC core

4. b a c kn e x th o m e Reuse Model tester SoC core

5. b a c kn e x th o m e Reuse Model tester SoC core

6. b a c kn e x th o m e Revisão dos principais objetivos e fatores de sucesso Improve the reuse the on-chip network as test access mechanism n minimal area overhead n zero pin overhead n feasible test time Power consumption is an issue? Optimal set of BISTed cores? Goal

7. b a c kn e x th o m e Revisão dos principais objetivos e fatores de sucesso n NoC-based Test n Power consumption calculation n Modified scheduling n Considering BISTed cores n Experimental Results n Final Remarks Outline

8. b a c kn e x th o m e Access Paths Within the NoC CUT 1 CUT 2 input output

9. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 input

10. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 input

11. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 output

12. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 output

13. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 input

14. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 input

15. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 output

16. b a c kn e x th o m e Access Paths Within the NoC CUT CUT 2 CUT 1 output

17. b a c kn e x th o m e Parallelism Within the NoC CUT 1 CUT 2 input output input output

18. b a c kn e x th o m e Pipeline Within the NoC CUT 1 CUT 2 CUT 3 input output input

19. b a c kn e x th o m e Pipeline Within the NoC CUT 1 CUT 2 CUT 3 input output input output

20. b a c kn e x th o m e Pipeline Within the NoC CUT 1 CUT 2 CUT 3 input output input

21. b a c kn e x th o m e Pipeline Within the NoC CUT 1 CUT 2 CUT 3 input output BOTTLENECKS!

22. b a c kn e x th o m e Packets Scheduling CUT 1 CUT 2 CUT 3 input output

23. b a c kn e x th o m e Packets Scheduling CUT 1 CUT 2 CUT 3 input output

24. b a c kn e x th o m e Packets Scheduling CUT 1 CUT 2 CUT 3 input output

25. b a c kn e x th o m e Packets Scheduling CUT 1 CUT 2 CUT 3 input output

26. b a c kn e x th o m e Packets Scheduling CUT 1 CUT 2 CUT 3 input output

27. b a c kn e x th o m e Reuse Algorithm Define test packets Define access paths for each core Select a packet Find available access path Schedule packet

28. b a c kn e x th o m e Power Consumption Calculation Router Core 2 Router Core 3 Router Core 4 Router Core 5 Router Core 6 wrapper Router Core 1

29. b a c kn e x th o m e Power Consumption Calculation Router Core 2 Router Core 3 Router Core 4 Router Core 5 Router Core 6 wrapper Router Core 1

30. b a c kn e x th o m e Power Consumption Calculation Router Core 2 Router Core 3 Router Core 4 Router Core 5 Router Core 6 wrapper Router Core 1 F(#ffs, #gates, switching rate) per cycle (any frequency) per packet

31. b a c kn e x th o m e Power Consumption Calculation Router Core 2 Router Core 3 Router Core 4 Router Core 5 Router Core 6 wrapper Router Core 1 F(length,width,switching rate) per cycle (any frequency)

32. b a c kn e x th o m e Power Consumption Calculation Router Core 2 Router Core 3 Router Core 4 Router Core 5 Router Core 6 wrapper Router Core 1 F(#ffs, #gates, switching rate) per cycle (any frequency) per pattern

33. b a c kn e x th o m e Power Consumption of One Packet CUT CUT 1 input 4*PW(router) + 3*PW(channel) + PW(CUT+wrapper)

34. b a c kn e x th o m e Power-Aware Scheduling

35. b a c kn e x th o m e Power-Aware Scheduling

36. b a c kn e x th o m e Power-Aware Scheduling

37. b a c kn e x th o m e Experimental Setup n SOCIN Network –under development at UFRGS –Grid topology –32-bit channels –deterministic routing (XY) n ITC02 SoC Test Benchmarks –d695, g1023 –Placement for synthetic applications

38. b a c kn e x th o m e Experimental Results - d695 Cores consumption >> wrapper consumption Test time Power Limit

39. b a c kn e x th o m e Experimental Results - g1023 Cores consumption >> wrapper consumption

40. b a c kn e x th o m e Experimental Results - d695 Cores consumption wrapper consumption Test time Power Limit

41. b a c kn e x th o m e Experimental Results - g1023 Cores consumption wrapper consumption

42. b a c kn e x th o m e BIST-Aware Scheduling n Each core has a BISTed version –30% more area –50% more power consumption –2x the number of test vectors n All cores BISTed –system test time = largest test time among cores –power consumption may be na issue

43. b a c kn e x th o m e BIST-Aware Scheduling 1) All cores BISTed –maximum parallelization –minimum test time? 2) Define test scheduling considering power constraints 3) Replace the core with largest test time by its external tested version 4) Repeat 2 and 3 until test time increases

44. b a c kn e x th o m e Experimental Results - p22810 No power constraints BISTed Cores

45. b a c kn e x th o m e Experimental Results - p22810 No power constraints BISTed Cores

46. b a c kn e x th o m e Experimental Results - p22810 No power constraints BISTed Cores

47. b a c kn e x th o m e Experimental Results - p22810 Multiple BIST model BISTed Cores

48. b a c kn e x th o m e Final Remarks n Alternative TAM for NoC-based SoCs n good trade-off test time x area X pin overhead even under power constraints (ETW03) n Selection of the optimal set of BISTed cores for test time minimization (TRP03) n Further selection of the best BIST method for the cores in the system