1. A Survey of Dynamically Reconfigurable FPGA Devices
Surbhi Singhal

2. Basic FPGA structure

3. Selecting a Target FPGA
Factors to be considered:
Dynamic reconfigurability
Reconfiguration time
Partial vs Full reconfiguration
Granularity

4. Dynamic reconfigurability
The ability of a FPGA to modify operation during runtime.
Correct FPGA selection very important.
The primary advantages of run-time reconfiguration in devices are reduced power consumption, hardware reuse and flexibility.
Main problem is the speed of reconfiguration.

5. Granularity Two main architectures:
Course grained: smaller number of larger, more powerful logic blocks
Advantage:
Faster because of easy routing
Fine grained : consists of a large number of small logic blacks
Good utilization
Easy conversion to ASIC

6. Xilinx Virtex Architecture
Architecture is coarse grained
Basic cell of the Virtex FPGA is configurable logic block(CLB)
CLB contains circuitry that allows it to efficiently perform arithmetic
LUT’s can be configured as SRAM cells
Contains programmable input output blocks (IOBs) interconnected to the CLBs

7. Xilinx Configurable Logic Block

8. Configuration of Xilinx Virtex
Fully and Partially reconfigurable
Module-Based partial reconfiguration
Distinct portions of an FPGA are referred to as reconfigurable modules.
Used for independent design applications
Small-Bit Manipulations
accomplished by making a small change to the design
Switching configuration is fast as bitstream difference is smaller than device difference.

9. Lattice ORCA Architecture
Coarse grained architecture
Four basic elements: programmable logic cells (PLCs), programmable input/output cells (PIOs), embedded block RAMs (EBRs), and system-level features.
Programmable functional unit (PFU) is the basic functional unit containing eight 4-input LUTs, 8 Iatches/FFs and one additional flip-flop for arithmetic functions

10. Lattice OCRA block diagram

11. Configuration of Lattice ORCA
Fully and Partially reconfigurable
Partial reconfiguration is done by setting a bitstream option that tells the FPGA to not reset the entire configuration
Options available to allow one portion of FPGA to remain in operation while the other is being reconfigured
Off chip reconfiguration

12. Atmel AT40K Architecture
Fine Grained architecture
Symmetrical array of identical cells
Distributed 10 ns SRAM capability
8-sided core cells with direct horizontal, vertical, and diagonal cell-to-cell connection
Small cells lead to large number of cells which leads to greater functionality
Each cell can implement 2 Boolean operations of 3 inputs or 1 operation of 4 inputs

13. AT40K Device Overview

14. Configuration of Atmel AT40K
Fully and Partially reconfigurable
Off chip reconfigeration
Configuration data transferred in either Master mode, slave mode or Synchronous RAM mode
Master mode:
Auto configuring.
The Master Mode uses an internal oscillator to provide the configuration clock for clocking configuration data
Synchronous RAM mode:
Device receives a 32-bit wide bit stream
It is a memory mapped address space.
User has full read/write access

15. Slave mode: configuration is always initiated by an extenal signal.
Slave Serial Mode the device receives serial configuration data
Slave Parallel mode the device receives either 8-bit wide or 16-bit wide parallel data.

16. AItera APEX 20K Architecture
Architecture is coarse grained
It combines LUT-based, product-term-based and memory into one device
Signal interconnections are provided by the Fast Track interconect
Consist of an array of MegaLAB structures
Each MegaLAB structure consists of a group of logic array blocks (LABs), one Embedded System Block (ESB), and a MegaLAB interconnect
Each LE contains a four-input LUT that can implement any function of four variables.

17. APEX 20K interconnect structure

18. MegaLAB structure

19. AItera APEX 20K configuration
Only Fully reconfigurable
During operation, it stores its data in SRAM cells.
Active configuration: both the target and the configuration device generate both control and synchronization signals
Passive configuration: device uses microprocessor to control the configuration process
Off chip reconfiguration

20. Conclusion
Wide variety of dynamically reconfigurable FPGA devices available today
Reconfiguration time of partial reconfiguration is much smaller (~4-5 ms) than full reconfiguration(~12 ms)

21. Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-Time Systems
Marisha Rawlins

22. Introduction
Run time partial reconfiguration is useful to designers who want to develop applications demanding adaptive and flexible hardware
Using partial reconfiguration can result in power and area savings
An intelligent system is needed to manage reconfiguration in order to save power and meet timing constrains in real time systems 22

23. Basic FPGA Layout

24. Partial Reconfiguration

25. Advantages of Dynamic Reconfiguration
Power/Size/Cost Reduction
Hardware Reuse
Obsolescence Avoidance
Application Portability 25

26. Slot Based Dynamically Reconfigurable System

27. Basic System Approach Address assignment
Each module is assigned a default address during design time
New modules are assigned valid logic addresses within the legal address range when they are loaded 27

28. Basic System Approach Transferring data from modules
The bus arbiter calls every existing address
If the module’s busy signal is asserted the arbiter selects the next address
The module’s request signal is asserted if the module wants to send data
Transferring data to modules
The main controller asserts a Data-In signal if external data is available for the selected module 28

29. Basic System Approach Data transfer schemes Replacing modules
The main controller knows the module’s data transfer time
A time stamp is sent before the data
Replacing modules
If a module not currently configured on the FPGA is needed an unused module is replaced
A context-save is done using data and state I/O lines
Data and state is transferred to local memory of the main controller 29

30. Basic System Approach Bus Realization Interfaces are in a fixed place
All modules can be implemented in every possible function column 30

31. Initial Results Using partial reconfiguration
The application can be implemented on XCV200E instead of XCV300E
Smaller area
Lower power
Lower cost
Can meet timing constraints for a real-time system 31

32. Power Consumed During Reconfiguration

33. Power Consumed During Reconfiguration

34. Conclusions
It is possible to use dynamic partial reconfiguration to save both power and area
An intelligent run time system is needed to ensure that power is saved and that timing constraints are meet when using partial reconfiguration for real time systems
Measuring power consumed during partial reconfiguration aids in determining the design of the run time system and the feasibility of using dynamic partial reconfiguration 34

35. Runtime FPGA Partial Reconfiguration
Shaon Yousuf

36. Outline Benefits of Fields-Programmable gate arrays (FPGAs)
Overview of Partial Reconfiguration (PR) in FPGAs
Partial Reconfiguration in the Xilinx Virtex-4
Software-Defined Radio and Partial Reconfiguration
What is Software-Defined Radio?
Why PR is applicable to Software-Define Radio?
PR designs of Software-Defined Radios (SDR)
Conclusions

37. Why FPGAs are being used?
FPGAs are now being used as replacement for application specific integrated circuits (ASICs) for many space-based applications
FPGAs provide:
Reconfigurable Architectures
Low Cost solution
Rapid Development Times
Additional benefits in each new generation other than expected larger size and faster speed

38. Design exploration on Latest FPGAs
Exploration and evaluation of designs with latest FPGAs can be difficult
Continuous endeavor as performance and capabilities improve significantly with each release
Each vendors products can have different characteristics and utilities
Often there are unique capabilities
Thus side by side evaluation of designs among different products are not straightforward
One such advancement of particular importance is partial reconfiguration (PR)
Three Vendors provide some degree of this feature
Xilinx
Atmel
Lattice

39. What is Partial Reconfiguration?
Partial reconfiguration (PR) allows the ability to reconfigure a portion of an FPGA
Real advantage arises when PR is done during runtime also know as dynamic reconfiguration
Dynamic Reconfiguration allows the reconfiguration of a portion of an FPGA while the remainder continues operating without any loss of data
Two types of Regions
Static – Keeps operating
Reconfigurable – Can be reconfigured with a new module
Central Controlling Agent
ICAP
Mem controller
Module A
Module B
Module C
Module D
Static modules
Reconfigurable Modules (PRMs)
Modules: A & B
PRR 1
PRR 2
FPGA
Static modules
Static region
Modules: C & D

40. Partial Reconfiguration in Virtex-4
Exploration of Partial Reconfiguration for a design requires significant knowledge on targeted Device
Xilinx’s FPGA’s are widespread, so the Virtex-4 Family was chosen as the example FPGA
Need to evaluate current performance and limitations
Reconfiguration speeds and methods
Design Hierarchy limitations related to PR Modules (PRMs) and number of allowed PR regions

41. Virtex-4 LX15 FPGA Layout Overall Structure
CLBs – Configurable logic blocks
IOBs – Input-output buffers
DSP48s – Xilinx’s digital signal processing units
BRAMs – Block Random Access Memories
FIFOs – First-in First-out buffers
DCMs – Digital Clock Managers
CLBs
IOBs
DSP48s
BRAMS and FIFOs
DCMs and Clock Dist.
Figure 1. Virtex-4 LX15 FPGA layout

42. Virtex-4 Reconfiguration
FPGA is reconfigured by writing bits into configuration Memory (CM)
Configuration data is organized into frames that target specific areas of the FPGA through frame addresses
To reconfigure any portion of that frame the partial bitstreams contain configuration data for a whole frame
Reconfiguration times highly depend on the size and organization of the PR regions
Virtex-II allowed column based PR only
Virtex-4’s allow arbitrarily sized PR regions
Virtex-4 Frames
Composed of bit words
The LX15 has 3,740 frames
Four methods of reconfiguring a device, each has applications where desirable
Externally
Serial configuration port
JTAG (Boundary Scan) port
SelectMap port
Internally
Though the Internal configuration access port (ICAP) using an embedded microcontroller or state machine

43. Reconfiguration Speeds
Table 1 shows a summary of Configuration Speeds for the four options
Table 2 shows example configurations sizes and times for the four options
Values were based on estimates of Xilinx’s PlanAhead Software when targeting an approximate PR region slice utilization of 90%
Table 1. Summary of Configuration Options
Table 2. Example Configuration Sizes and Times to Configure with JTAG and SelectMAP/ICAP

44. Reconfiguration using an Embedded Microcontroller
Many Xilinx FPGAs have Embedded hard processor cores
Processor core has the ability to process C/C++ code
Makes reconfigurable designs extremely flexible since no need for external control
Reconfiguration Steps
Reconfiguration is triggered within the FPGA
Processor core loads the desired configuration data from external reconfiguration memory
This could be from ROM, Flash, static Ram loaded at startup or filled up by the FPGA itself
Processor reconfigures the PR region through the ICAP primitive
Figure 2. PR design using embedded microcontroller

45. PR Design Hierarchy
Flow from Hardware Description Language (HDL) to configuration bitstream is extremely complicated
Top-level module should contain sub-modules that are either static or reconfigurable
All communications except global signals such as clock must be explicitly declared using 8-bit bus macros
Current PR design flow allows multiple Partial reconfiguration regions
One Partial Reconfiguration for PRM A and one for PRM B
Figure 3. Example design showing two PR regions

46. PR Design Hierarchy Cont.
Required hierarchy adds significant amount of effort when converting an existing static design into one that is ready for PR
Having all PRM at the top level will often require routing many signals to and from another module deep within the main static module
a) Hierarchical view before PR partitioning
b) Required design partitioning
Figure 4. Transceiver design with turbo coding and concatenated convolutional + Reed-Solomon coding

47. PR software Support
Initially there was very little software support to assist in generating PR designs and bitstreams
Recently
Xilinx’s EA PR flow with the integration of the Xilinx’s PlanAhead tool greatly mitigates the complicacies of PR

48. Software-Defined Radios and Partial Reconfiguration
Determining whether PR is appropriate for a given application depends heavily upon the FPGA family
One such field PR can be applied for great advantage is software-define radio

49. Why Software Defined Radio?
Wireless communication abilities are becoming ubiquitous in the latest generation of portable electronics
Cell phones, Camera’s, MP3 players etc.
Satellites need an overwhelming number of communication standards to communicate with these wide array of devices
Hardware designs that attempt to provide compatibility with current standards will likely become obsolete shortly after their release
Solution: Use Software-defined radios (SDR’s)
SDRs run on a generic hardware platform that allow communication parameters to be defined by the software during runtime
Some common communication functions affected by the parameters are modulation, demodulation, filtering, frequency selection and frequency hopping

50. What is Software-Defined Radio?
SDRs split into three basic sections
Radio Frequency (RF) Section
Acts as a transceiver, performing conversion up or down to the intermediate frequency
Intermediate Frequency (IF) Section
Performs all the necessary signal processing , modulation, demodulation, filtering etc
Base-Band Section
Performs the processing of the digital data, i.e, data payload assembled or disassembled
Reconfigurable SDR Design
Basically, creating a modular design on an FPGA that can load the desired functions as needed
The reconfigurable nature on an FPGA allows reconfiguring the functionality of a specific block while the reminder of the design continues to function
Provides a unique opportunity to create an extremely flexible and compact design
Figure 5. Block Diagram of a generic Software-defined radio

51. PR designs for Software Defined Radios
Three SDR types where the application of PR were studied
Simplex Spread-Spectrum Transceiver with FEC
Dynamic Bandwidth Resource Allocation Transceiver
Cognitive Radio

52. Simplex Spread-Spectrum Transceiver with FEC
Simplex transceiver
Transmit or receive capabilities used at a given time but never at the same time
Assuming Waveform requires
Forward error checking (FEC)
Direct-sequence spread spectrum (DSSS)
Two PR regions defined
One for Tx modulator or the Rx demodulator
One for the Tx FEC encoder, the Rx DSSS acquisition engine, or the Rx FEC decoder
Figure 6. Simplex Spread-Spectrum Transceiver with FEC

53. Dynamic Bandwidth Resource Allocation Transceiver
Dynamic Bandwidth Resource Allocation (DBRA) systems alter communication waveform dynamically to match channel conditions
Adjust configuration to keep bit error rate at a current threshold
Four PR regions Defined
One for Tx Binary Phase Shift-Keying (BPSK) or Tx Gaussian minimum shift keying (GMSK)
One for Turbo encoder or Convolution encoder, followed by Reed-Solomon (RS) encoding
One for Rx BPSK or Rx 8-ary Phase shift-keying (8PSK)
One for Turbo Decoder or concatenated Viterbi, followed by RS decoder
Figure 7. Dynamic bandwidth resource allocation transceiver

54. Cognitive Radio Receiver
Steps for Cognitive Radio (CR) function
Scan the available spectrum using an FTT
Locate energy
create a channel that attempts to match the spectral shape
Perform modulation recognition
Try to demodulate
One PR region
One for Modulation recognition and one for the Demodulator
FFT Module is left static as spectrum is frequently monitored
If reconfiguration speed is very fast, FFT can also be made reconfigurable
Figure 8. Cognitive radio receiver

55. Conclusions
Exploring the usefulness of PR in the field of software define radio has shown both its feasibility and benefits
Design time overhead involved when creating a PR design is acceptable but requires progressing though a slow learning curve before any results are obtained
Full benefits of PR will not be evident until it becomes commonplace in industry and vendors place more resources on supporting the PR design flow and keeping documentation up to date
However, the adaptivity of PR combined with the desire for SDR’s make a strong argument for pursuing PR.

56. Questions?

57. Thanks 