1. 1 VLSI Digital System Design Clocking

2. 2 Clocked System Basic structure Q DlogicQ D clock

3. 3 Fundamental Timing Parameters Positive edge-triggered flip-flop clock D Q

4. 4 Static Storage Elements Level-sensitive latch Edge-triggered master-slave flip-flop RS latch T flip-flop JK flip-flop

5. 5 Level-Sensitive Latch clock Q D Q D Negative level-sensitive latchPositive level-sensitive latch 0 1 0 1

6. 6 Positive Edge-Triggered Master-Slave Flip-Flop clock Q D 0 1 0 1 Master stageSlave stage

7. 7 RS Latch Q ~Q R S Q R S

8. 8 RS Latch Behavior SRQ 00Maintain previous state 010 101 11Undefined

9. 9 Incorrect T Flip-Flop clock Q 0 1 0 1 ~clear

10. 10 JK Flip-Flop Behavior JKQ 00Maintain previous state 010 101 11Toggle

11. 11 Level-Sensitive Latch Circuit clock Q D Level-sensitive latch 0 1 ~clock clock ~clock clock D Q Level-sensitive latch circuit

12. 12 Jamb Latch Circuit Jamb latch circuit ~Q D ~clock clock weak clock Q D ~clock clock Level-sensitive latch circuit

13. 13 Jamb Latch Circuit Design Replace feedback transmission gate with: Feedback inverter that is weaker than driving inverter Either: Decrease gain of feedback transistors –Increase L to decrease W/L Or: Increase gain of driving inverter

14. 14 Level-Sensitive Latch Circuit clock Q D ~clock clock Level-sensitive latch circuit clock Q D ~clock clock Redrawn level-sensitive latch circuit

15. 15 Buffered Level-Sensitive Latch Circuit clock Q D ~clock clock Redrawn level-sensitive latch circuit clock Q D ~clock clock Buffered level-sensitive latch circuit

16. 16 Detailed Buffered Level-Sensitive Latch Circuit clock Q D ~clock clock Buffered level-sensitive latch circuit clock Q D ~clock clock Buffered level-sensitive latch circuit, details

17. 17 Simplified Buffered Level-Sensitive Latch Circuit Q ~clock clock Buffered level-sensitive latch circuit, clock Q D ~clock clock Buffered level-sensitive latch circuit D ~clock clock with one connection deleted

18. 18 Dynamic Latches Time before refresh required depends upon leakage current Leakage current depends upon temperature Refresh even if behavior independent of stored value –Intermediate voltage level causes driven gates to draw current

19. 19 Clock Skew Q D C clock R Input pad

20. 20 Phase-Locked Loop Q D C clock PLL R Input pad

21. 21 Higher On-Chip Clock Frequency Q D C clock Div by 4 R Input pad PLL

22. 22 Phase-Locked Loop Block Diagram Filter Phase Detector Voltage Controlled Oscillator (VCO) Charge Pump Div by 4 Reference clock f in 4 * f in

23. 23 Probability of Upset Upset is the case of a storage element resolving to the wrong data value p= probability of upset = T 0 exp( - t r /t c ) T 0 = constant for the circuit design t c = time constant of resolution for the element = 1/GB = 1/(gain-bandwidth product) = constant for the circuit design

24. 24 Resolve Time, t r p= probability of upset = T 0 exp( - t r /t c ) t r = resolve time = time allowed for the storage element to resolve its state

25. 25 Probability of Upset Example T 0 = 0.1 s t c = 0.1 ns t r = 5.0 ns p= T 0 exp( - t r /t c ) = 0.1 * exp( -5.0/0.1 ) = 0.1 * exp( -50 ) = 0.1 * 1.9 * 10 -22 = 1.9 * 10 -23 Hz -1 Hz -1 s -1

26. 26 Mean Time Between Upsets MTBU= 1/( p * f c * f d ) p= probability of upset = T 0 exp( - t r /t c ) f c = clock frequency f d = data frequency

27. 27 MTBU Example p= 1.9 * 10 -23 Hz -1 Hz -1 s -1 f c = 100 MHz f d = 1 Mhz MTBU= 1/( p * f c * f d ) = 1/( 1.9 * 10 -23 * 10 8 * 10 6 ) = 1/( 1.9 * 10 -9 ) = 5.2 * 10 8 s = 16.4 years

28. 28 MTBU Perspective May have thousands of storage elements in a system May have thousands or millions of systems Provide margin of safety Maximize resolve time, t r

29. 29 Synchronizer Q D clock synchronized dataasynchronous data