1. 1 Power Management for High- speed Digital Systems Tao Zhao Electrical and Computing Engineering University of Idaho

2. 2 Motivation Smaller CMOS process brings faster switching time and lower V DD Power efficiency: static power consumption goes larger Power integrity: voltage noise margin becomes smaller

3. 3 How high is high-speed? Options: A. >1KHz B. >1MHz C. >1GHz It is when the passive components come in to play and even dominate the behavior of the circuits, the speed is high-speed High-speed digital system study is a study of the behavior of passive components

4. 4 Where are the passive circuits?

5. 5 Reduce V DD and increase V SS The problem becomes more serious when V DD goes lower Low impedance path between V DD and ground All frequencies of interest have to be covered Where are the passive circuits?

6. 6 How high do we have to care? Clock frequencies Signal Rise and Fall Time F KNEE =

7. 7 How high do we have to care? F KNEE = =500MHz T RISE =1ns F CLOCK =25MHz

8. 32-bit reconfigurable data processor, always a slave Maximize throughput, minimize control Multiple chips can be tiled to extend the size of the data path Current revision: 250nm process, 250K gates, runs at 25MHz, radiation-hardened 16 pairs of power and ground pins Field Programmable Processing Array

9. Serves as memory for the FPPA Include memory address control and 1MB RAM Like the FPPA, multiple RMMs can be tiled too RMM has only been simulated in software, but not been fabricated Assume the RMM has the same DC characteristics as the FPPA Reconfigurable Memory Module

10. 10 The Reconfigurable Platform

11. 11 Power Domain

12. Power Budget DC characteristic Target impedance

13. 13 Power Delivery Path

14. 14 Voltage Regulator Linear vs. Switching

15. 15 low efficiency low noise level cheap high efficiency high noise level expensive Voltage Regulator Linear Voltage Regulator Switching Voltage Regulator Supply desired voltage level Supply enough current Radiation hardened

16. 16 Wiring Impedance Wiring Resistance is negligible V=L*di/dt

17. 17 Decoupling Capacitor (Decap)

18. 18 Bulk Capacitor ESL Self-resonant frequency

19. 19 Parallel Ceramic Capacitors Self-resonant at higher frequency parallelism

20. 20 Ceramic Capacitor Selection

21. 21 Ceramic Capacitor Array

22. 22 Ceramic Capacitor Array

23. 23 Decoupling Capacitor Network

24. 24 Dynamic Power Management Subsystems can be powered up and down in runtime High-side load switch

25. 25 Power-up Challenge Free from big current spike, monotonic voltage ramp-up Don’t upset the rest of the system Decoupling capacitor network adds load capacitance: internal capacitance (nF); decap (μF) Inrush current: I=C*dV/dt I=C*dv/dt=5 μF*2.5V/1 μs=12.5A

26. 26 Soft Start-up Small dV/dt rate substantially reduces inrush current Soft start: longer time, less current The rise time of the gate voltage determines the turn-on time of the PMOS

27. 27 Slew-rate Controllable High-side Load Switch

28. 28 Reduce Inrush Current

29. 29 Sequencing and Voltage Supervisor Commercial products -- ADM1066 Programmable Sequencer 10 channels for sequencing and 12 channels for supervising Contain a state machine to control the sequencing and supervising

30. 30 Conclusion High-speed digital design focuses on the behaviors of passive circuits Digital system design trends: lower VDD requires better power integrity and power efficiency

31. 31 Conclusion Design flow: Power budget Choose the right voltage regulator Design decoupling capacitor network to filter voltage noise Use soft-start and sequencing start-up to prevent big inrush current Voltage supervisor

32. 32 Future Work Measurement: accurate numbers Board level interconnection: LVDS Lower voltage: Better power integrity

33. Dr. Gregory Donohoe Dr. Kenneth Hass Dr. Robert Rinker All the FPPA team members Acknowledgement

34. 34