1. The High Voltage/High Power FET (HiVP)
Amin K. Ezzeddine & Ho C. Huang
Amcom Communications, Inc.
Clarksburg, Maryland, USA

2. Presentation Outline Why high voltage device?
Traditional high voltage approaches
New High Voltage/ High Power (HiVP) configuration
Implementation of a 14V & 28V GaAs MMIC HiVP
Conclusion

3. Why High Voltage Device?
Some applications need high voltage:
Phase arrays
Satellite transmitters
No DC-to-DC converter
Low breakdown voltage in semiconductors materials such as: GaAs, AlGaAs, InP.
High power

4. FET High Voltage Configurations
Traditional high voltage device configurations:
DC series/ RF parallel
DC series/ multi-stage
New High Voltage/high Power device (HiVP)

5. DC Series/RF Parallel Configuration
INPUT
MATCHING
OUTPUT
Power Divider
Power Combiner
Vgg
Vds
2Vds
3Vds
Vdd = 4Vds
RF IN
RF OUT
Choke
Bypass

6. DC-Series/Cascaded-Stages Configuration
OUTPUT
MATCHING
INPUT
MATCING
Vds
2Vds
INTERSTAGE
Vgs
RF in
Choke
Bypass
RF out

7. New High Voltage/ High Power (HiVP)
Equivalent performance to a single device: - Efficiency - Power
Higher gain
High voltage bias
Scaled I-V characteristics
Power combiner

8. 4-Cell High Voltage/ High Power (HiVP)
OUTPUT
MATCHING
INPUT
Vgs
Vd3=3Vds
Vdd = 4Vds
RF IN
RF OUT
Vd2=2Vds
Vd1=Vds
FET1 (W/4)
FET2 (W/4)
FET3 (W/4)
FET4 (W/4) C1 C2 C3 R4 R3 R2 R1
Vg4=3Vds+ Vgs
Vg3=2Vds+ Vgs
Vg2=Vds+ Vgs
Vg1=Vgs

9. I-V Characteristics of a 4-Cell (4 x 3mm) HiVP Device

10. 4-Cells HiVP Voltage Waveforms
Vin
Vd3=3Vm
Vdd = 4Vm
Vd2=2Vm
Vd1=Vm C1 C2 C3 R4 R3 R2 R1
Zopt

11. Impedance Optimization of Common Gate FET
Drain
Source
CN+1
Gate CN
Zsource, N
Zopt, N = Z source, N+1
(N+1)th
FET
Nth
Zopt, N+1
Z source, N  1/gm (Cgs+ C N) / CN
gm is FET transconductance
Cgs is FET gate-to-source capacitance

12. HiVP Configuration Features
High voltage bias: Vdd = Vds x N
Lower Current by 1/N factor compared to regular FET with equivalent periphery
Higher optimum output impedance by N2 factor
Higher input impedance
Higher gain by factor of N
Broadband matching
Simple & compact configuration
Concept applicable to LDMOS and MOSFET to achieve very high power

13. Power & IP3 for 14V Hybrid HiVP at 1GHz
P1dB =35dBm
Efficiency = 25%
IP3 = 45dBm
@ 1.0GHz

14. 14V/2-Cells HiVP MMIC ( 2 x 2mm device)
S-Parameters
Chip Layout
P1dB =31dBm
Efficiency = 35%
IP3 = 46dBm
@ 3.5GHz

15. Pout & Efficiency of 2 x 2mm HiVP at 3.5GHz

16. IP3 & IP5 of 2 x 2mm HiVP at 3.5GHz

17. 28V/4-Cells HiVP MMIC (4 x 1mm device)
S-Parameters
Chip Layout
P1dB =31dBm
Efficiency = 32%
IP3 = 45dBm
@ 1GHz

18. 28V/4-Cells HiVP in Parallel (4 x 3mm device)
4 x 3mm Chip
Package Device
P1dB =35dBm
Efficiency = 27%
IP3 = 50dBm
@ 2.15GHz

19. Power & Efficiency of 4 x 3mm HiVP at 2.15GHz

20. IP3 of a 4 x 3mm HiVP at 2.15GHz

21. IP3 at 2.15GHz for 4 x 3mm HiVP versus 12 mm FET

22. 24V/4-Cell High Power pHemt HiVP (4 x24mm)
4 x 24mm Chip
P1dB =43dBm
Efficiency = 30%
IP3 = 57dBm
@ 1.5GHz
4 x 6mm Chip

23. Power & Efficiency of 4 x 24mm pHemt HiVP at 1.5GHz

24. IP3 of 4 x 24mm pHEMT HiVP at 1.5GHz

25. Conclusion
A simple DC series/RF series device (HiVP) for high voltage operation is presented
This simple new device behaves as an RF combiner
New device has good linearity and broadband performance
HiVP concept could be applied to GaN and Silicon FETs to push the power to kW ranges