1. Memory Management Paging &Segmentation CS311, CS350 & CS550

2. CS552 Implementation Issues in Paging Four times when OS involved with paging 1. Process creation  determine program’s resident-set size  create page table 2. Process execution  MMU reset for new process  TLB flushed 3. Page fault time  determine (virtual) address causing fault  swap target page out, needed page in 4. Process termination time  release page table, pages 2

3. CS552 Page Fault Handling (1) 1. Hardware traps to kernel, t1 is interrupted 2. Mode switch into kernel: Privilege mode ON, Interrupts OFF, Protection OFF 3. General (users) registers saved 4. OS determines which (virtual) page needed 5. OS checks validity of (virtual) address 6. OS Seeks target/victim; if victim dirty, then write it to disk 7. OS schedules I/O request for new page from disk 8. OS dispatches another task (t n ), while waiting 9. Page-in I/O completes, t2 registers saved 10. Page tables updated 11. Faulting instruction backed up to when it began 12. Faulting process scheduled 13. Registers restored 14. Program (t1) continues 3

4. CS552 Locking Pages in Memory  (Virtual) memory and I/O occasionally interact  Proc issues call for read from device into buffer  while waiting for I/O, another processes starts up  has a page fault  buffer for the first proc may be chosen to be paged out  Need to specify some pages locked  exempted from being target pages 4

5. CS552 Separation of Policy and Mechanism Page fault handling with an external pager 5

6. CS552 Segmentation (Pt1)  One-dimensional address space with growing tables  One table may bump into another (solution?) 6

7. CS552 Segmentation (Pt2) Allows each table to grow or shrink, independently 7

8. CS552 Segmentation (Pt3) Comparison of paging and segmentation 8

9. CS552 Implementation of Pure Segmentation (a)-(d) Development of checkerboarding (external fragmentation) (e) Removal of the checkerboarding by compaction 9

10. CS552 Segmentation with Paging: MULTICS (Pt1)  Descriptor segment points to page tables  Segment descriptor – numbers are field lengths 10

11. CS552 Segmentation with Paging: MULTICS (Pt2) Conversion of a 2-part MULTICS address into a main memory address 11

12. CS552 Segmentation with Paging: Pentium (Pt1) A Pentium selector GDT = Global Descriptor Table LDT = Local Descriptor Table Similar to MULTICS, but addresses a number of different design goals  Code segment descriptor  Data segments differ slightly 12

13. CS552 Segmentation with Paging: Pentium (Pt2) Conversion of a (selector, offset) pair to a linear address 13

14. CS552 Segmentation with Paging: Pentium (Pt3) Mapping of a linear address onto a physical address 14

15. CS552 Segmentation with Paging: Pentium (Pt4) Protection on the Pentium Level 15

16. CS552 References  Chapters 8 and 9 :OS Concepts, Silberschatz, Galvin, Gagne  Chapter 4: Modern Operating Systems, Andrew S. Tanenbaum  X86 architecture  http://en.wikipedia.org/wiki/Memory_segment  Memory segment  http://en.wikipedia.org/wiki/X86  Memory model  http://en.wikipedia.org/wiki/Memory_model  IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture  http://www.intel.com/design/pentium4/manuals/index_new.htm 16