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Introduction to VLSI Programming TU/e course 2IN30 http://www.win.tue.nl/~johanl/educ/2IN30/ Lecture 3: Control Handshake Circuits (2) http://www.win.tue.nl/~johanl/educ/2IN30/ Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir. Ad Peeters]
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-162 TU/e Time table 2005 dateclass | labsubject Aug. 302 | 0 hoursintro; VLSI Sep. 63 | 0 hourshandshake circuits Sep. 133 | 0 hourshandshake circuits assignment Sep. 203 | 0 hoursTangram Sep. 27no lecture Oct. 4 no lecture Oct. 111 | 2 hoursdemo, fifos, registers | deadline assignment Oct. 181 | 2 hoursdesign cases; Oct. 251 | 2 hoursDLX introduction Nov. 11 | 2 hourslow-cost DLX Nov. 81 | 2 hourshigh-speed DLX Nov. 29deadline final report
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-163 TU/e Last Week – Lecture 2
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-164 TU/e VLSI metrics dimensionless quantities (0.12 m CMOS): Aareagate equivalent (8 m 2, or 120,000 geq/mm 2 ) Ttimegate delay (0.2 nanosecond) Eenergytransition (0.5 picojoule)
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-165 TU/e Handshake signaling active sidepassive side request a r acknowledge a k request a r time event sequence: a r a k a r a k
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-166 TU/e Useful shorthands Four-phase handshakes –a = [ar] ; ak ; [ ar] ; ak –a = ar ; [ak] ; ar ; [ ak] Two-phase handshakes –a = [ar] ; ak –a = [ ar] ; ak –a = ar ; [ak] –a = ar ; [ ak]
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-167 TU/e Some handshake components Repeater : [a : [b ; b ] ] Mixer : [ [ a : c ; [a : c ] [] b : c ; [b : c ] ] ] Sequencer : [[a : (b ; b ; c ) ] ; [a : c ]] a b a ; b c | a c b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-168 TU/e Handshake components: realization From handshake notation to gate network in 8 steps: 1 Specify component in handshake notation. 2 Expand to individual boolean variables (wires). 3 Introduce auxiliary state variables (if required). 4 Derive a set of production rules that implements this refined specification. 5 Make production rules more symmetric (cheaper). 6 Verify isochronic forks. 7 Verify initialization constraints. 8 Analyze time, area, and energy.
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-169 TU/e Mixer realization Behavior: [ [ a : c ; a : c [] b : c ; b : c ] ] Restriction: a r b r must hold at all times! Expansion: [ [ [a r ] ; c r ; [c k ] ; a k ; [ a r ] ; c r ; [ c k ] ; a k [] [b r ] ; c r ; [c k ] ; b k ; [ b r ] ; c r ; [ c k ] ; b k ] ] a c b |
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1610 TU/e Mixer realization Production rules: a r c k a k b r c k b k c k a k c k b k a r b r c r a r b r c r More symmetric production rules: a r c k a k a r c k a k a r c k a k a r c k a k premature a k more expensive | a c b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1611 TU/e Mixer realizations Mixer: area, delay, energy Area: 6 gate equivalents Delay per cycle: 8 gate delays Energy per cycle: 8 transitions
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1612 TU/e This Week – Lecture 3
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1613 TU/e Join realization Behavior: [ [ a : b : c ; a : b : c ] ] Expansion: [ [ a r ] ; [ b r ] ; c r ; [ c k ] ; b k ; a k ; [ a r ] ; [ b r ] ; c r ; [ c k ] ; b k ; a k ] = [ [ a r b r ] ; c r ; [ c k ] ; b k , a k ; [ a r b r ] ; c r ; [ c k ] ; b k , a k ] a c b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1614 TU/e Join realization *[ [ a r b r ] ; c r ; [ c k ] ; b k , a k ; [ a r b r ] ; c r ; [ c k ] ; b k , a k ] Production rules: c k a k c k b k c k a k c k b k a r b r c r a r b r c r fork C-element a c b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1615 TU/e Join realization c k a k c k b k c k a k c k b k a r b r c r a r b r c r Join: area, delay, energy Area: 2 gate equivalents Delay per cycle: 4 gate delays Energy per cycle: 4 transitions C arar brbr crcr ckck akak bkbk
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1616 TU/e Sequencer realization Specification: [(a : (b ; b ; c ) ) ; (a : c )] Expansion: [ [a r ] ; b r ; [b k ] ; b r ; [ b k ] ; c r ; [c k ] ; a k ; [ a r ] ; c r ; [ c k ] ; a k ] a ; b c
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1617 TU/e Expansion Sequencer: [ [a r ] ; b r ; [b k ] ; b r ; [ b k ] ; c r ; [c k ] ; a k ; [ a r ] ; c r ; [ c k ] ; a k ] Sequencer realization decompose into wire c k a k , c k a k and a remainder (S-element): [ [a r ] ; b r ; [b k ] ; b r ; [ b k ] ; c r ; [ a r ] ; c r ]
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1618 TU/e Sequencer realization Expansion S-element: [ [a r ] ; b r ; [b k ] ; b r ; [ b k ] ; c r ; [ a r ] ; c r ] Production rules S-element ?: a r b r b k c r b k b r a r c r What is wrong?
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1619 TU/e Sequencer realization Introduction of auxiliary state variable x [ [ a r ] ; b r ; [b k ] ; x ; [x] ; b r ; [ b k ] ; c r ; [ a r ] ; x ; [ x] ; c r ] Production rules S-element: a r b k x x a r b r x b k c r a r x x a r b r x b k c r Note: a r in guard for x to prevent conflicts during initialization
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1620 TU/e Sequencer realization using state-transition tables (1) [ [a r ] ; b r ; [b k ] ; b r ; [ b k ] ; c r ; [c k ] ; a k ; [ a r ] ; c r ; [ c k ] ; a k ] State encoding not unique
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1621 TU/e Sequencer realization using state-transition tables (2) [ [a r ] ; b r ; [b k ] ; x ; [x] ; b r ; [ b k ] ; c r ; [c k ] ; a k ; [ a r ] ; x ; [ x] ; c r ; [ c k ] ; a k ] State encoding unique
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1622 TU/e Sequencer realization using state-transition tables (3) a r b k x a r x a k c k a k c k Note: a r in guard for x to prevent conflicts during initialization
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1623 TU/e Sequencer realization using state-transition tables (4) a r x b r a r x b r b k x c r b k x c r
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1624 TU/e Sequencer realization Sequencer: area, delay, energy Area: 5 gate equivalents Delay per cycle: 12 gate delays (8 with optimized C-element) Energy per cycle: 12 transitions (10 with optimized C-element) xx arar bkbk brbr crcr ckck akak
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1625 TU/e Time for a break
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1626 TU/e Parallel realization [ a : ((b ; b ) || (c c )) ; a ] Cf. Join component Expansion: [ [a r ] ; ( (b r ; [b k ] ; b r ; [ b k ]) || (c r ; [c k ] ; c r ; [ c k ]) ) ; a k ; [ a r ] ; a k ] a || b c
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1627 TU/e Parallel realization [ a : ( (b ; b ) || (c c ) ) ; a ] Expansion: [ [a r ] ; ( (b r ; [b k ] ; b r ; [ b k ]) || (c r ; [c k ] ; c r ; [ c k ]) ) ; a k ; [ a r ] ; a k ] Auxiliary variables x,y: [ [a r ] ; ( (b r ; [b k ] ; x ; [x] ; b r ; [ b k ]) || (c r ; [c k ] ; y ; [y] ; c r ; [ c k ]) ) ; a k ; [ a r ] ; x , y ; [ x y] ; a k ] a || b c
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1628 TU/e Parallel realization [ [a r ] ; ( (b r ; [b k ] ; x ; [x] ; b r ; [ b k ]) || (c r ; [c k ] ; y ; [y] ; c r ; [ c k ]) ) ; a k ; [ a r ] ; x , y ; [ x y] ; a k ] Production rules: b k x c k y a r b k x a r c k y a r x b r a r y c r a r x b r a r y c r x y a k x y a k reshuffling applied to a k
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1629 TU/e Modulo-N counter Specification (regular expression): (a N b)* N=1: repeater + sequencer N>1: rewrite spec as: (a N mod 2 (a 2 ) N div 2 b)* Specification Header: (a N mod 2 (a a 2 )* b b)* Head N mod 2 Modulo (N div2) counter a b a b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1630 TU/e Modulo-N counter: Header Rewriting specification of Header cell (L = N mod 2): (a L (a a 2 )* b b)* = ( (a L a a 2-L )* a L b b)* = ( a L a a 2-L + a L b b)* = ( a L ( a a 2-L + b b) )*
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1631 TU/e Modulo-N counter: Header For N is odd (i.e. L=1) forever do a ; sel a ; a [] b ; b les od Rewriting ( a L ( a a 2-L + b b) )* in Tangram For N is even (i.e. L=0) forever do sel a ; a ; a [] b ; b les od
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1632 TU/e Header: handshake circuit L=0L=1
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1633 TU/e Selector (specification) [ (a :[ b : x ; b ; d [] c : x ; c ; e ] ) ; (a : [x d [] x e ] ) ] a [|][|] c e d b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1634 TU/e Self initialization Initialization problem: how to force (gate-level) handshake circuit into an initial state? Aim: self initialization: –no “reset” wire –circuit proceeds to initial state when all inputs low.
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1635 TU/e Self initialization: requirements Component specification: R1. Initial state of component must be quiescent. R2. Component must be “initial when closed”. Component implementations: R3. When all inputs low, component must become initial. R4. When passive inputs low, active outputs become low. Handshake circuit: R5. Activity graph must be acyclic (nodes: components; edges: act pas directed channels)
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1636 TU/e Self initialization: theorem A handshake circuit satisfying R5 and with component satisfying R1 - R4 is self initializable. All Tangram handshake components satisfy R1-R4. All compiled handshake circuits satisfy R5.
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1637 TU/e Self initialization: proof (induction) i A° i B i D° i E G satisfies R4 o B o C H satisfies R3; o C = i C° o C° o D° o E G satisfies R3 o A° GH A° D° C° BB CC EE R5 allows decomposition: all handshake. wires low R2, R1 all handshake. components initial
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1638 TU/e Excercise: selector realization [ (a :[ b : x ; b ; d [] c : x ; c ; e ]) ; (a : [x d [] x e ] ) ] a [|][|] c e d b Follow the 8 realization steps!! (it is ok to skip the isochronic-fork analysis) Note: x is a specification variable and is not necessarily part of a realization.
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1639 TU/e Assignment : duplicator realization Behavior: [[a : (b ; b ; b ) ] ; [a : b ]] Required:realization with 2 sequential gates. (sequencer + mixer requires 3 sequential gates) Follow the 8 realization steps!! (it is ok to skip the isochronic-fork analysis) Add comparison with sequencer+mixer realization. #2 a b
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Philips Research, Kees van Berkel, Ad Peeters, 2003-09-1640 TU/e Next week: lecture 4 Outline: Data encoding; push and pull handshakes Tangram assignment command Handshake components: handshake latch, transferrer, multiplexer, adder Handshake circuits & Tangram programs: fifo buffers and shift registers
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