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COMP541 Datapath & Single-Cycle MIPS
Montek Singh Oct 27, 2014
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Topics Complete the datapath Add control to it
Create a full single-cycle MIPS! Reading Chapter 7 Review MIPS assembly language Chapter 6 of course textbook Or, Patterson Hennessy (inside front flap)
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A MIPS CPU reset clk clk pc memwrite Instr Memory MIPS CPU Data Memory
dataadr writedata instr readdata
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Top-Level: MIPS CPU + memories
reset clk Top-level module MIPS CPU Instr Memory Data pc instr memwrite dataadr readdata writedata clk reset We will add I/O devices (display, keyboard, etc.) later
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Top-Level MIPS: Verilog
module top(input clk, reset, output … ); // add signals here for debugging // we will add I/O later wire [31:0] pc, instr, readdata, writedata, dataadr; wire memwrite; mips mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata); // processor imem imem(pc[31:0], instr); // instr memory // send full PC to imem dmem dmem(clk, memwrite, dataadr, writedata, readdata); // data memory endmodule
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One level down: Inside MIPS
Datapath: components that store or process data registers, ALU, multiplexors, sign-extension, etc. we will regard memories as outside the CPU, so not part of the core datapath Control: components that tell datapath what to do and when control logic (FSMs or combinational look-up tables) MIPS CPU Control ALUFN, regwrite, regdst… opcode, func, flagZ … MIPS Datapath Instr Memory Data pc instr memwrite dataadr readdata writedata clk reset clk
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One level down: Inside MIPS
module mips(input clk, reset, output [31:0] pc, input [31:0] instr, output memwrite, output [31:0] dataaddr, writedata, input [31:0] readdata); wire memtoreg, branch, pcsrc, alusrc, regdst, regwrite, jump; wire [4:0] ALUFN; wire flagZ; controller c(instr[31:26], instr[5:0], flagZ, memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite, jump, ALUFN); datapath dp(clk, reset, memtoreg, pcsrc, ALUFN, flagZ, pc, instr, dataddr, writedata, readdata); endmodule NOTE: This is may need changes before you use it for your lab assignment
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Review: MIPS instruction types
Three instruction formats: R-Type: register operands I-Type: immediate operand J-Type: for jumps
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R-Type instructions Register-type 3 register operands: Other fields:
rs, rt: source registers rd: destination register Other fields: op: the operation code or opcode (0 for R-type instructions) funct: the function together, op and funct tell the computer which operation to perform shamt: the shift amount for shift instructions, otherwise it is 0
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R-Type Examples Note the order of registers in the assembly code:
add rd, rs, rt
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I-Type instructions Immediate-type 3 operands: op: the opcode
rs, rt: register operands imm: 16-bit two’s complement immediate
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I-Type Examples Note the differing order of registers in the assembly and machine codes: addi rt, rs, imm lw rt, imm(rs) sw rt, imm(rs)
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J-Type instructions Jump-type 26-bit address operand (addr)
Used for jump instructions (j)
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Review: Instruction Formats
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MIPS State Elements We will fill out the datapath and control logic for basic single cycle MIPS first the datapath then the control logic
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Single-Cycle Datapath: lw
Let’s start by implementing lw instruction How does lw work? STEP 1: Fetch instruction
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Single-Cycle Datapath: lw
STEP 2: Read source operands from register file
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Single-Cycle Datapath: lw
STEP 3: Sign-extend the immediate NOTE: Sign Extension is done conditionally in our MIPS there are signed and unsigned instructions (e.g., ADD vs. XOR)
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Single-Cycle Datapath: lw
STEP 4: Compute the memory address Note ALUControl: ours will be different
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Single-Cycle Datapath: lw
STEP 5: Read data from memory and write it back to register file
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Single-Cycle Datapath: lw
STEP 6: Determine the address of the next instruction
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Let’s be Clear: CPU is Single-Cycle!
Although the slides said “STEP” … … all those operations are performed in one cycle!!! Let’s look at sw next … … and then R-type instructions
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Single-Cycle Datapath: sw
Write data in rt to memory nothing is written back into the register file
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Single-Cycle Datapath: R-type instr
R-Type instructions: Read from rs and rt Write ALUResult to register file Write to rd (instead of rt)
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Single-Cycle Datapath: beq
Determine whether values in rs and rt are equal Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4)
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Complete Single-Cycle Processor (w/control)
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Control Unit Generally as shown below
but some differences because our ALU is more sophisticated Note: Zero flag is input to control, and PCSrc is generated here! flagZ PCSrc Note: This will be different for our full-feature ALU! Note: This will be 5 bits for our full-feature ALU!
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Review: Lightweight ALU from book
Function 000 A & B 001 A | B 010 A + B 011 not used 100 A & ~B 101 A | ~B 110 A - B 111 SLT
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Review: Lightweight ALU from book
Function 000 A & B 001 A | B 010 A + B 011 not used 100 A & ~B 101 A | ~B 110 A - B 111 SLT
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Review: Our “full feature” ALU
Our ALU from Lab 3 (with support for comparisons) A B Result Bidirectional Shifter Boolean Add/Sub Sub Bool Shft Math Sub Bool Shft Math OP 0 XX A+B 1 XX A-B 1 X A LT B 1 X A LTU B X B<<A X B>>A X B>>>A X A & B X A | B X A ^ B X A | B 5-bit ALUFN <? Flags N,V,C Bool0 Z Flag
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Review: R-Type instructions
Register-type 3 register operands: rs, rt: source registers rd: destination register Other fields: op: the operation code or opcode (0 for R-type instructions) funct: the function together, op and funct tell the computer which operation to perform shamt: the shift amount for shift instructions, otherwise it is 0
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Controller (2 modules) module controller(input [5:0] op, funct,
input flagZ, output memtoreg, memwrite, output pcsrc, alusrc, output regdst, regwrite, output jump, output [2:0] alucontrol); // 5 bit ALUFN for our ALU!! wire [1:0] aluop; // This will be different for our ALU wire branch; // See NOTE on next slide maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop); aludec ad(funct, aluop, alucontrol); assign pcsrc = branch & (op == beq ? flagZ : ~flagZ); // handle both beq and bne endmodule flagsZ PCSrc
![Controller (2 modules) module controller(input [5:0] op, funct,](http://slideplayer.com./slide/3853933/13/images/32/Controller+%282+modules%29+module+controller%28input+%5B5%3A0%5D+op%2C+funct%2C.jpg "input flagZ, output memtoreg, memwrite, output pcsrc, alusrc, output regdst, regwrite, output jump, output [2:0] alucontrol); // 5 bit ALUFN for our ALU!! wire [1:0] aluop; // This will be different for our ALU. wire branch; // See NOTE on next slide. maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop); aludec ad(funct, aluop, alucontrol); assign pcsrc = branch & (op == beq flagZ : ~flagZ); // handle both beq and bne. endmodule. flagsZ. PCSrc.")
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Note on Controller Implementation
For Lab: we will merge the functionality of the main decoder and ALU decoder into one so, okay not to partition into two submodules
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This entire coding may be different in our design
Main Decoder module maindec(input [5:0] op, output memtoreg, memwrite, branch, alusrc, output regdst, regwrite, jump, output [1:0] aluop); // different for our ALU reg [8:0] controls; assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} = controls; case(op) 6'b000000: controls <= 9'b ; //Rtype 6'b100011: controls <= 9'b ; //LW 6'b101011: controls <= 9'b ; //SW 6'b000100: controls <= 9'b ; //BEQ 6'b001000: controls <= 9'b ; //ADDI 6'b000010: controls <= 9'b ; //J default: controls <= 9'bxxxxxxxxx; //TIP: put controls for NOP here! endcase endmodule Why do this? This entire coding may be different in our design
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This entire coding will be different in our design
ALU Decoder module aludec(input [5:0] funct, input [1:0] aluop, output reg [2:0] alucontrol); // 5 bits for our ALU!! case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; // ADD 6'b100010: alucontrol <= 3'b110; // SUB 6'b100100: alucontrol <= 3'b000; // AND 6'b100101: alucontrol <= 3'b001; // OR 6'b101010: alucontrol <= 3'b111; // SLT default: alucontrol <= 3'bxxx; // ??? endcase endmodule This entire coding will be different in our design
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Control Unit: ALU Decoder
This entire coding will be different in our design ALUOp1:0 Meaning 00 Add 01 Subtract 10 Look at Funct 11 Not Used ALUOp1:0 Funct ALUControl2:0 00 X 010 (Add) X1 110 (Subtract) 1X (add) (sub) (and) 000 (And) (or) 001 (Or) (slt) 111 (SLT)
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Control Unit: Main Decoder
Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 R-type 000000 1 … lw 100011 sw 101011 X beq 000100
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Note on controller The actual number and names of control signals may be somewhat different in our/your design compared to the one given in the book because we are implementing more features/instructions SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU!
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Single-Cycle Datapath Example: or
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Extended Functionality: addi
No change to datapath
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Control Unit: addi 1 … X R-type 000000 lw 100011 sw 101011 beq 000100
Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 R-type 000000 1 … lw 100011 sw 101011 X beq 000100 addi 001000
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Adding Jumps: j
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Control Unit: Main Decoder
Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 Jump R-type 000000 1 … lw 100011 sw 101011 X beq 000100 j XX
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Summary We learned about a complete MIPS CPU
NOTE: Many details are different… … from what you will implement in the lab our lab MIPS has more features every single line of Verilog you take from these slides must be carefully vetted! Next class: We will look at performance of single-cycle MIPS We will look at multi-cycle MIPS to improve performance Next lab: Implement single-cycle CPU!
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